{"title":"用于源同步存储器件实时测试的2GS/s, 10ps分辨率CMOS差分时间-数字转换器","authors":"Kazuhiro Yamamoto, M. Suda, T. Okayasu","doi":"10.1109/CICC.2007.4405700","DOIUrl":null,"url":null,"abstract":"A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.","PeriodicalId":130106,"journal":{"name":"2007 IEEE Custom Integrated Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device\",\"authors\":\"Kazuhiro Yamamoto, M. Suda, T. Okayasu\",\"doi\":\"10.1109/CICC.2007.4405700\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.\",\"PeriodicalId\":130106,\"journal\":{\"name\":\"2007 IEEE Custom Integrated Circuits Conference\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2007.4405700\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2007.4405700","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
摘要
介绍了一种采用0.18 μ m CMOS工艺制作的差分时间-数字转换器(TDC)，用于源同步器件测试。它的最大采样率为2.133 GS/s，可变分辨率为10-40 ps，测量范围无限，INL为8.5 ps(pk-pk)，抖动为18.3 ps(pk-pk)。它可以应用于无死区时间的抖动直方图测量，因为它连续检测所有的过渡时间。此外，本文还提出了将该TDC应用于ADC或DAC的可能性。
2GS/s, 10ps Resolution CMOS Differential Time-to-Digital Converter for Real-Time Testing of Source-Synchronous Memory Device
A differential time-to-digital converter (TDC), fabricated in 0.18 mum CMOS process, for source-synchronous device testing is demonstrated. It exhibits a maximum sampling rate of 2.133 GS/s, a variable resolution of 10-40 ps, an infinite measurement range, an INL of 8.5 ps(pk-pk), and a jitter of 18.3 ps(pk-pk). It is available to be applied to the jitter histogram measurement without dead-time because it detects all transition timing continuously. Furthermore, a possible application of this TDC to ADC or DAC is suggested.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
