Design of an 128-point FFT processor for OFDM applications

Important issues in designing ASICs are short design time, flexibility, reuse of building blocks, and reliability. These factors can be met by using automatic design tools and standard-cell design. The major drawback with this approach is the attainable circuit performance. In this paper we present an efficient design approach which combines the short design time and flexibility of the standard-cell approach and the high performance of the unconstrained cell layout style. A 128-point FFT/IFFT chip aimed at OFDM applications has successfully been designed using this approach. Further, a modular architecture is proposed that is scalable with respect to the throughput requirements. The throughput scaling can also be utilized to reduce power consumption.