A self-aligned counter well-doping technology utilizing channeling ion implantation and its application to 0.25 /spl mu/m CMOS process

A new self-aligned counter doping technology intentionally utilizing the channeling effect of ion implantation is presented. A 50%-70% reduction of junction capacitance is achieved. Further, a 18.3% improvement in simulated propagation delay time is demonstrated for a 0.25 /spl mu/m CMOS inverter chain under 0.9 V operation.