AVS2快速模式内决策算法及硬件设计

Hao Xie, Kaiyang Liu, Yang Zhao, Xiao Zheng, Xianguo Qing
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引用次数: 0

摘要

AVS2是中国提出的一种视频编码标准,它采用了33种帧内预测模式来提高编码性能,但计算复杂度急剧增加。为了降低AVS2模内决策的复杂性,使AVS2硬件编码器满足实时性要求,本文提出了AVS2模内快速决策算法和硬件设计。实验结果表明,本文提出的模内决策算法和硬件设计能够满足1920x1080@60fps在300MHz时钟频率下的吞吐量要求。通过在Vivado HLS平台上使用赛灵思FPGA XC7K325T 900进行合成,仅消耗FPGA资源中10%的LUT、5%的FF、5%的BRAM和6%的DSP即可满足设计要求。
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Intra Fast Mode Decision Algorithm and Hardware Design for AVS2
AVS2 is a kind of video coding standard proposed by China, it adopts 33 intra prediction modes to improve coding performance, while the computational complexity has increased dramatically. In order to reduce the complexity of AVS2 intra mode decision and make the AVS2 hardware encoder meet real-time requirements, this paper proposes the AVS2 intra fast mode decision algorithm and hardware design. The experimental results show that the intra mode decision algorithm and hardware design proposed in this paper can meet the throughput requirement of 1920x1080@60fps at a clock frequency of 300MHz. By using Xilinx FPGA XC7K325T 900 on the Vivado HLS platform for synthesis, only 10% of the LUT, 5% of FF, 5% of BRAM, and 6% of DSP in FPGA resources are consumed to meet the design requirements.
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