A very low-cost multi-mode Reed-Solomon decoder based on Peterson-Gorenstein-Zierler algorithm

Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Among various RS decoding algorithms, the Peterson-Gorenstein-Zierler (PGZ) in general has the least computational complexity for small t values. However, unlike the iterative approaches (e.g., Berlekamp-Massey algorithm), it will encounter divide-by-zero problems in solving multiple t values. We propose a multi-mode hardware architecture for error number ranging from zero to three. We first propose a cost-down technique to reduce the hardware complexity of a t=3 decoder. Then, we perform an algorithmic-level derivation to identify the configurable feature of our design. With the manipulations, we are able to perform multi-mode RS decoding in one unified VLSI architecture with a very simple control scheme. The very low cost and simple datapath make our design a good choice in small-footprint embedded VLSI systems such as error control coding (ECC) in memory systems.