A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis

The authors consider the problem of diagnosing implementation errors in synchronous sequential circuits described by state tables. The diagnosis problem is formulated so as to provide the erroneously implemented entries of the state table, which are useful for the purposes of debugging the synthesis procedure. The diagnosis procedure developed is not limited to a specific error model and no bound is set on error multiplicity. Experimental results are presented to show the effectiveness of this procedure. The experiments indicate that state tables with certain properties make their implementations more amenable to diagnosis than others. These properties are used as guidelines for synthesis.<>