先进CMOS节点的新型热载流子AC-DC设计指南

C. Guérin, V. Huard, C. Parthasarathy, J. Roux, A. Bravaix, E. Vincent
{"title":"先进CMOS节点的新型热载流子AC-DC设计指南","authors":"C. Guérin, V. Huard, C. Parthasarathy, J. Roux, A. Bravaix, E. Vincent","doi":"10.1109/RELPHY.2008.4559016","DOIUrl":null,"url":null,"abstract":"The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.","PeriodicalId":187696,"journal":{"name":"2008 IEEE International Reliability Physics Symposium","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-07-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Novel hot-carrier AC-DC design guidelines for advanced CMOS nodes\",\"authors\":\"C. Guérin, V. Huard, C. Parthasarathy, J. Roux, A. Bravaix, E. Vincent\",\"doi\":\"10.1109/RELPHY.2008.4559016\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.\",\"PeriodicalId\":187696,\"journal\":{\"name\":\"2008 IEEE International Reliability Physics Symposium\",\"volume\":\"53 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-07-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 IEEE International Reliability Physics Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RELPHY.2008.4559016\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 IEEE International Reliability Physics Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RELPHY.2008.4559016","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10

摘要

由于电源电压(Vdd)和通道长度(L)不再以相似的比例缩放,因此对电路寿命和器件直流热载流子(HC)应力寿命之间关系的理解对于先进节点变得越来越重要。本文提出了一种新的方法,通过结合精细化的晶体管HC建模,晶圆级可靠性(WLR)和高温工作寿命测试(HTOL)的实验结果和模拟来解决HC风险评估。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Novel hot-carrier AC-DC design guidelines for advanced CMOS nodes
The understanding of the relationship between circuit lifetime and device DC hot carrier (HC) stress lifetime is becoming increasingly important for advanced nodes since supply voltage (Vdd) and channel length (L) do not scale anymore in similar proportions. This paper proposes a novel approach to tackle HC risk assessment through a combination of refined transistor HC modeling, Wafer Level Reliability (WLR) & High Temperature Operating Lifetest (HTOL) experimental results and simulations.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Degradation effects in a-Si:H thin film transistors and their impact on circuit performance High-robust ESD protection structure with embedded SCR in high-voltage CMOS process New insight into tantalum pentoxide Metal-Insulator-Metal (MIM) capacitors: Leakage current modeling, self-heating, reliability assessment and industrial applications Electron energy loss spectrum application for failure mechanism investigation in semiconductor failure analysis Characterization of stress-voiding of Cu / Low-k vias attached to narrow lines
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1