采用标准CMOS技术的高可靠性高压CMOS晶体管

Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003 Pub Date : 2003-07-07 DOI:10.1109/IPFA.2003.1222714

W.F. Sun, L. Shi

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引用次数: 5

摘要

提出了一种新的高可靠性HV-CMOS (High Voltage CMOS)，兼容0.6/spl mu/m规则的标准Bulk-Silicon (BS) CMOS工艺。通过在HV-PMOS(高压PMOS)和HV-DNMOS(高压双扩散NMOS)上添加p阱来蚀刻不需要的厚栅氧化膜，从而大大提高了HV-CMOS的可靠性。所提出的高压cmos击穿电压超过100 V，可用于功率驱动ic等。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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High reliability HV-CMOS transistors in standard CMOS technology

A novel high-reliability HV-CMOS (High Voltage CMOS) compatible with 0.6/spl mu/m rules standard Bulk-Silicon (BS) CMOS process was proposed. The reliability of the HV-CMOS is greatly improved by adding the p-well to HV-PMOS (High Voltage PMOS) for etching the unwanted thick-gate-oxide film and that to HV-DNMOS (High Voltage Double-Diffusion NMOS) for preventing punch-through. The breakdown voltage of the presented HV-CMOS exceeds 100 V, which can be used in power driver ICs, etc.

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Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003

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