Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222749
P. Ratchev, B. Vandevelde, I. De Wolf
The authors study the reliability and failure mechanisms of eutectic SnAgCu solder interconnects on NiAu surface finish. As a comparision, the reliability and failure mechanism of standard SnPb solder joints on SiAu surface finish is studied as well. The similarities and differences in the failure modes for both solders are analysed and discussed.
{"title":"Reliability and failure analysis of SnAgCu solder interconnections on NiAu surface finish","authors":"P. Ratchev, B. Vandevelde, I. De Wolf","doi":"10.1109/IPFA.2003.1222749","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222749","url":null,"abstract":"The authors study the reliability and failure mechanisms of eutectic SnAgCu solder interconnects on NiAu surface finish. As a comparision, the reliability and failure mechanism of standard SnPb solder joints on SiAu surface finish is studied as well. The similarities and differences in the failure modes for both solders are analysed and discussed.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115694495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222712
Z.G. Song, S. K. Loh, M. Gunawardana, C. Oh, S. Redkar
In this paper, we present some defects encountered and the involved failure analysis methods for these defects during copper metallization development.
本文介绍了铜金属化开发过程中遇到的一些缺陷及其失效分析方法。
{"title":"Unique defects and analyses with copper damascene process for multilevel metallization","authors":"Z.G. Song, S. K. Loh, M. Gunawardana, C. Oh, S. Redkar","doi":"10.1109/IPFA.2003.1222712","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222712","url":null,"abstract":"In this paper, we present some defects encountered and the involved failure analysis methods for these defects during copper metallization development.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124418188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222747
J. Semmens, L. W. Kessler
FFT frequency domain imaging has been used to reveal features down to only Angstroms in thickness, which is substantially below the accepted wavelength limit of the resolution, in applications such as wafer bonding, flip chips, and MEMS.
{"title":"Higher resolution acoustic images using frequency domain imaging","authors":"J. Semmens, L. W. Kessler","doi":"10.1109/IPFA.2003.1222747","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222747","url":null,"abstract":"FFT frequency domain imaging has been used to reveal features down to only Angstroms in thickness, which is substantially below the accepted wavelength limit of the resolution, in applications such as wafer bonding, flip chips, and MEMS.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122925119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222737
J. Chuang, J.C. Lee
Conductive Atomic Force microscopy (C-AFM) is a popular technique for the electrical characterization of dielectric film and gate oxide integrity. In this article, C-AFM has been successfully applied to fault identification in contact level and the discrimination of various contact types. The current mapping of C-AFM can easily isolate faulty contacts. In addition, it also provide I/V curve for failure root cause judgment.
{"title":"Conductive atomic force microscopy application on leaky contact analysis and characterization","authors":"J. Chuang, J.C. Lee","doi":"10.1109/IPFA.2003.1222737","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222737","url":null,"abstract":"Conductive Atomic Force microscopy (C-AFM) is a popular technique for the electrical characterization of dielectric film and gate oxide integrity. In this article, C-AFM has been successfully applied to fault identification in contact level and the discrimination of various contact types. The current mapping of C-AFM can easily isolate faulty contacts. In addition, it also provide I/V curve for failure root cause judgment.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120921124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222741
C.W. Chang, C. L. Gan, C. Thompson, K. Pey, W. Choi, M. H. Chua
Failure mechanisms observed in electromigration (EM)-stressed dual damascene Cu/SiO/sub 2/ interconnect trees were studied by stressing at fixed conditions for a short time followed by stressing with increasing current to induce Joule heating. Similar failure sites as those observed in samples stressed at normal EM conditions were found. This suggests that Joule heating can be used to accelerate some EM failure mechanisms that occur in normal EM experiments. Finite element method (FEM) simulation showed that the failure mechanisms could be due to Joule heating of Ta diffusion barrier after fully-spanning void was formed. The probabilistic existence of the post-stress 'volcano craters' and melt patches is highly dependent on the void growth mechanism during EM stressing.
{"title":"Joule heating-assisted electromigration failure mechanisms for dual damascene Cu/SiO/sub 2/ interconnects","authors":"C.W. Chang, C. L. Gan, C. Thompson, K. Pey, W. Choi, M. H. Chua","doi":"10.1109/IPFA.2003.1222741","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222741","url":null,"abstract":"Failure mechanisms observed in electromigration (EM)-stressed dual damascene Cu/SiO/sub 2/ interconnect trees were studied by stressing at fixed conditions for a short time followed by stressing with increasing current to induce Joule heating. Similar failure sites as those observed in samples stressed at normal EM conditions were found. This suggests that Joule heating can be used to accelerate some EM failure mechanisms that occur in normal EM experiments. Finite element method (FEM) simulation showed that the failure mechanisms could be due to Joule heating of Ta diffusion barrier after fully-spanning void was formed. The probabilistic existence of the post-stress 'volcano craters' and melt patches is highly dependent on the void growth mechanism during EM stressing.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130817371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222755
C. Maiti, S. Samanta, G. Dalapati, S. Chatterjee
In this paper, we investigate the SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ gate stack as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained-Si.
{"title":"Electrical characterization of SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ stacked gate oxides on strained-Si","authors":"C. Maiti, S. Samanta, G. Dalapati, S. Chatterjee","doi":"10.1109/IPFA.2003.1222755","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222755","url":null,"abstract":"In this paper, we investigate the SiO/sub x/N/sub y//Ta/sub 2/O/sub 5/ gate stack as a possible candidate for future strained-Si CMOS applications and demonstrate and possibility of integration of high-k gate dielectric with the strained-Si.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133184969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222763
Huixian Wu, B. Hooghan, J. Cargo
In this work, physical FA techniques including deprocessing and cross section analysis have been developed and applied to Cu/low k technology. Deprocessing techniques discussed include: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. For the cross-section analysis of copper/low k samples, focused ion beam and mechanical polishing techniques have been developed and studied. Failure Analysis (FA) challenges and new failure modes, reliability issues will also be addressed.
{"title":"Physical Failure Analysis techniques for Cu/low k technology","authors":"Huixian Wu, B. Hooghan, J. Cargo","doi":"10.1109/IPFA.2003.1222763","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222763","url":null,"abstract":"In this work, physical FA techniques including deprocessing and cross section analysis have been developed and applied to Cu/low k technology. Deprocessing techniques discussed include: wet chemical etching, reactive ion etching (RIE), parallel polishing, chemical mechanical polishing (CMP) and combination of these techniques. For the cross-section analysis of copper/low k samples, focused ion beam and mechanical polishing techniques have been developed and studied. Failure Analysis (FA) challenges and new failure modes, reliability issues will also be addressed.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127837961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222746
K. M. Chong, H. K. Lim, Chin Seng. Ong
In this paper, the V-shape silicon cracking was identified due to extreme bending to substrate. The fracture initialise once the stress on silicon exceed the silicon strength.
本文确定了由于衬底极端弯曲而产生的v型硅裂纹。一旦硅上的应力超过硅的强度，断裂就会初始化。
{"title":"Flip chip silicon fracture mechanism with 3-point bend metrology on flip chip ball grid array","authors":"K. M. Chong, H. K. Lim, Chin Seng. Ong","doi":"10.1109/IPFA.2003.1222746","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222746","url":null,"abstract":"In this paper, the V-shape silicon cracking was identified due to extreme bending to substrate. The fracture initialise once the stress on silicon exceed the silicon strength.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121098292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222762
T. Joseph, K. Varn, N. Arnold, D. Griffiths
Recent development of a vertical transistor deep trench capacitor DRAM cell revealed several new failure mechanisms and proved to be a challenge to traditional failure analysis techniques. The development was done on two test vehicles, an existing planar transistor 256 Mb design with an 8F/sup 2/ 175 nm ground rule cell was modified to use the vertical transistor and a 512 Mb 110 nm design was implemented with the vertical transistor. This paper gives examples of failure mechanisms found during the early phases of the development cycle and discusses the application of failure analysis techniques to the unique structures on the vertical transistor DRAM technology.
{"title":"Vertical transistor deep trench DRAM failure analysis and failure mechanisms","authors":"T. Joseph, K. Varn, N. Arnold, D. Griffiths","doi":"10.1109/IPFA.2003.1222762","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222762","url":null,"abstract":"Recent development of a vertical transistor deep trench capacitor DRAM cell revealed several new failure mechanisms and proved to be a challenge to traditional failure analysis techniques. The development was done on two test vehicles, an existing planar transistor 256 Mb design with an 8F/sup 2/ 175 nm ground rule cell was modified to use the vertical transistor and a 512 Mb 110 nm design was implemented with the vertical transistor. This paper gives examples of failure mechanisms found during the early phases of the development cycle and discusses the application of failure analysis techniques to the unique structures on the vertical transistor DRAM technology.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131161137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2003-07-07DOI: 10.1109/IPFA.2003.1222710
T. Ning
Silicon CMOS is fast reaching its scaling limits. Nonetheless, silicon CMOS will remain the backbone technology for all digital designs. While attempts to extend the limits of CMOS will continue, there will also be increasing focus on other silicon technologies that can contribute significantly to system performance. Large amounts of high-performance on-chip memory are needed to minimize the performance penalty caused by the finite size of the cache memory. Large amounts of low-power NVRAM are needed for data storage in systems where magnetic disk storage is not available. High-performance and low-power mixed-signal technology is needed for wireless systems. Also, a truly non-volatile RAM could be a game changer to system designers.
{"title":"Silicon VLSI trends - what else besides scaling CMOS to its limit?","authors":"T. Ning","doi":"10.1109/IPFA.2003.1222710","DOIUrl":"https://doi.org/10.1109/IPFA.2003.1222710","url":null,"abstract":"Silicon CMOS is fast reaching its scaling limits. Nonetheless, silicon CMOS will remain the backbone technology for all digital designs. While attempts to extend the limits of CMOS will continue, there will also be increasing focus on other silicon technologies that can contribute significantly to system performance. Large amounts of high-performance on-chip memory are needed to minimize the performance penalty caused by the finite size of the cache memory. Large amounts of low-power NVRAM are needed for data storage in systems where magnetic disk storage is not available. High-performance and low-power mixed-signal technology is needed for wireless systems. Also, a truly non-volatile RAM could be a game changer to system designers.","PeriodicalId":266326,"journal":{"name":"Proceedings of the 10th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IPFA 2003","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2003-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129969065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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