{"title":"10位50MS/s流水线ADC的系统设计","authors":"Kehan Zhu, S. Balagopal, V. Saxena","doi":"10.1109/WMED.2013.6544508","DOIUrl":null,"url":null,"abstract":"A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.","PeriodicalId":134493,"journal":{"name":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Systematic design of 10-bit 50MS/s pipelined ADC\",\"authors\":\"Kehan Zhu, S. Balagopal, V. Saxena\",\"doi\":\"10.1109/WMED.2013.6544508\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.\",\"PeriodicalId\":134493,\"journal\":{\"name\":\"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WMED.2013.6544508\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Workshop on Microelectronics and Electron Devices (WMED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WMED.2013.6544508","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A systematical design analysis of a 10-bit 50MS/s pipelined ADC is presented. With an opamp-sharing technique, the power consumption is reduced drastically. Simulated in a 130-nm CMOS process, it achieves a 58.9dB signal-to-noise ratio (SNR), a 9.3 effective number of bits (ENOB), 64dB spurious free dynamic range (SFDR) with a sinusoid input of 4.858-MHz 1-Vpp at 50MS/s, and consumes less than 24 mW from a 1.2-V supply.
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