K. Shohji, T. Wada, K. Seki, T. Mutoh, T. Noda, Y. Kubota, T. Hagiwara, K. Shimohigashi
{"title":"一种基于内部电压发生器的1mbit闪存EEPROM自动擦除技术","authors":"K. Shohji, T. Wada, K. Seki, T. Mutoh, T. Noda, Y. Kubota, T. Hagiwara, K. Shimohigashi","doi":"10.1109/VLSIC.1990.111114","DOIUrl":null,"url":null,"abstract":"An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"77 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A novel automatic erase technique using an internal voltage generator for 1 Mbit flash EEPROM\",\"authors\":\"K. Shohji, T. Wada, K. Seki, T. Mutoh, T. Noda, Y. Kubota, T. Hagiwara, K. Shimohigashi\",\"doi\":\"10.1109/VLSIC.1990.111114\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described\",\"PeriodicalId\":239990,\"journal\":{\"name\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"volume\":\"77 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1990.111114\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111114","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel automatic erase technique using an internal voltage generator for 1 Mbit flash EEPROM
An on-chip automatic erase technique using an internal voltage generator has been developed and has proved to operate well in 1-Mb-flash EEPROM. This technology permits accurate control of erasure and guarantees the performance after erasure of the true single-transistor-per-cell type of flash EEPROM. Device implementation is described