{"title":"0.3 V电源,17 ppm/°C 3晶体管皮瓦参考电压","authors":"A. C. Oliveira, J. Caicedo, H. Klimach, S. Bampi","doi":"10.1109/LASCAS.2016.7451060","DOIUrl":null,"url":null,"abstract":"In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.","PeriodicalId":129875,"journal":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"0.3 V supply, 17 ppm/°C 3-transistor picowatt voltage reference\",\"authors\":\"A. C. Oliveira, J. Caicedo, H. Klimach, S. Bampi\",\"doi\":\"10.1109/LASCAS.2016.7451060\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.\",\"PeriodicalId\":129875,\"journal\":{\"name\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"volume\":\"34 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LASCAS.2016.7451060\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LASCAS.2016.7451060","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
0.3 V supply, 17 ppm/°C 3-transistor picowatt voltage reference
In this work a novel resistorless MOSFET 3-transistor voltage reference that operates in the picowatt range and occupies very small area is proposed. The circuit is based on a self-cascode structure that is biased in subthreshold condition using the leakage current provided by a reverse biased MOSFET diode. Its electrical behavior is analytically described and a design methodology is presented to allow the transistors sizing for optimal temperature compensation. Simulation results for a standard 130 nm CMOS process are presented to validated the proposed circuit topology. A reference voltage of 85 mV is obtained with a temperature coefficient (TC) of 17.4 ppm/°C and consuming only 7 pW under 0.3 V of power supply at room temperature. Monte Carlo analysis shows that the reference voltage σ/μ<; 3.3% and that 90% of the samples present TC<;50 ppm/°C without trimming.