A Clock Synthesis Algorithm for Hierarchical Chains of Homogeneous Clover-Leaves Clock Networks for Single Flux Quantum Logic Circuits

Single Flux Quantum (SFQ) is a promising option for high performance and low power supercomputing platforms. Nevertheless, timing uncertainty represents an obstacle to the design of high-frequency clock distribution networks. The hierarchical chains of homogeneous clover-leaves clocking, $(\mathrm{HC})^{2}\mathrm{LC}$. was proposed as an innovative solution to this challenge. This paper presents a novel algorithm for the physical implementation of $(\mathrm{HC})^{2}\mathrm{LC}$ networks. The proposed method models the (HC)2LC network as a directed graph with multiple cycles representing the synchronizing feedback signals. This graph is then transformed to a directed acyclic graph (DAG) by eliminating feedback edges. The physical location of the nodes in the generated DAG (such as splitters and C-junctions) in the Manhattan plane is calculated using a zero-skew clock embedding algorithm. Additionally, a novel mixed integer linear programming (MILP) based approach minimizes the maximum clock skew among the sinks of the clock network and the sum of the delay of the edges in feedback loops, simultaneously. Experimental results show that using the proposed approach, the average clock skew for five benchmark circuits is 4.6ps.