Design and Optimization of New Enhanced Vertical GaN Nanowire Transistor Using Sentaurus TCAD for Power Applications

A novel enhanced vertical GaN nanowire transistor structure is designed and optimized using the TCAD tool. The impact of the diameter, length, and doping concentration has been analyzed for the channel and drift region parts with and without surface traps. For the channel region, it has been observed that the device is Normally-OFF when the nanowire’s diameter and channel doping are less than 200 nm and 1×1017 cm−3, respectively. When considering a density of acceptor-type surface traps of 1×1013 cm−2.eV−1, the threshold voltage (Vth) has slightly increased. The breakdown voltage (VBR) of the device is found to increase as the length of the drift region increases and as the diameter of the nanowire decreases. Our simulation results show that the on-state resistance (RON) of the device increases drastically at low doping level of the drift region, when surface traps are taken into account. The threshold value of the doping level, above which RON remains small and insensitive to surface traps, increases as the nanowire diameter decreases.