{"title":"低温激活镓和锑离子注入浅结","authors":"S. Tavakoli, Kyoung-Eon Lee, S. Baek, H. Hwang","doi":"10.1109/IWJT.2004.1306770","DOIUrl":null,"url":null,"abstract":"Low-resistive n+/p and p+/n junctions were investigated using antimony and gallium conventional ion-implantation and low temperature rapid thermal annealing to be implemented in high-rmetal-electrode gate stack MOSFETs. Both dopant species completely regrew through solid phasevepitaxial regrowth (SPER) with low thermal budget and acceptable annealing time (at 600°C for 1 min). SPER resulted in highly activated junctions and acceptable leakage current without significant change in junction depth compared to as-implanted profile. The results indicated that Sb and Ga are proper candidates for shallow and low resistive source and drain extensions fabricated at low temperature for high-rMOSFET processing era.","PeriodicalId":342825,"journal":{"name":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low temperature activated Ga and Sb ion-implanted shallow junctions\",\"authors\":\"S. Tavakoli, Kyoung-Eon Lee, S. Baek, H. Hwang\",\"doi\":\"10.1109/IWJT.2004.1306770\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Low-resistive n+/p and p+/n junctions were investigated using antimony and gallium conventional ion-implantation and low temperature rapid thermal annealing to be implemented in high-rmetal-electrode gate stack MOSFETs. Both dopant species completely regrew through solid phasevepitaxial regrowth (SPER) with low thermal budget and acceptable annealing time (at 600°C for 1 min). SPER resulted in highly activated junctions and acceptable leakage current without significant change in junction depth compared to as-implanted profile. The results indicated that Sb and Ga are proper candidates for shallow and low resistive source and drain extensions fabricated at low temperature for high-rMOSFET processing era.\",\"PeriodicalId\":342825,\"journal\":{\"name\":\"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-03-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWJT.2004.1306770\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The Fourth International Workshop on Junction Technology, 2004. IWJT '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWJT.2004.1306770","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low temperature activated Ga and Sb ion-implanted shallow junctions
Low-resistive n+/p and p+/n junctions were investigated using antimony and gallium conventional ion-implantation and low temperature rapid thermal annealing to be implemented in high-rmetal-electrode gate stack MOSFETs. Both dopant species completely regrew through solid phasevepitaxial regrowth (SPER) with low thermal budget and acceptable annealing time (at 600°C for 1 min). SPER resulted in highly activated junctions and acceptable leakage current without significant change in junction depth compared to as-implanted profile. The results indicated that Sb and Ga are proper candidates for shallow and low resistive source and drain extensions fabricated at low temperature for high-rMOSFET processing era.