L. Ansari, B. Feldman, G. Fagas, J. Colinge, J. Greer
{"title":"无结硅纳米线晶体管的原子尺度模拟","authors":"L. Ansari, B. Feldman, G. Fagas, J. Colinge, J. Greer","doi":"10.1109/ULIS.2011.5757980","DOIUrl":null,"url":null,"abstract":"We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.","PeriodicalId":146779,"journal":{"name":"Ulis 2011 Ultimate Integration on Silicon","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-03-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Atomic scale simulation of a junctionless silicon nanowire transistor\",\"authors\":\"L. Ansari, B. Feldman, G. Fagas, J. Colinge, J. Greer\",\"doi\":\"10.1109/ULIS.2011.5757980\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.\",\"PeriodicalId\":146779,\"journal\":{\"name\":\"Ulis 2011 Ultimate Integration on Silicon\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-03-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Ulis 2011 Ultimate Integration on Silicon\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ULIS.2011.5757980\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Ulis 2011 Ultimate Integration on Silicon","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ULIS.2011.5757980","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Atomic scale simulation of a junctionless silicon nanowire transistor
We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
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