横向扩展(LatEx)主动用于改善60纳米以下DRAM时代的数据保留时间

ESSDERC 2007 - 37th European Solid State Device Research Conference Pub Date : 2007-09-01 DOI:10.1109/ESSDERC.2007.4430944

Sungsam Lee, Jong-Woo Park, Kwangwook Lee, S. Jang, Junhong Lee, H. Byun, Ilgweon Kim, Yongjin Choi, M.S. Shim, D. Song, Joosung Park, Tae-woo Lee, D.W. Shin, G. Jin, Kinam Kim

{"title":"横向扩展(LatEx)主动用于改善60纳米以下DRAM时代的数据保留时间","authors":"Sungsam Lee, Jong-Woo Park, Kwangwook Lee, S. Jang, Junhong Lee, H. Byun, Ilgweon Kim, Yongjin Choi, M.S. Shim, D. Song, Joosung Park, Tae-woo Lee, D.W. Shin, G. Jin, Kinam Kim","doi":"10.1109/ESSDERC.2007.4430944","DOIUrl":null,"url":null,"abstract":"A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era\",\"authors\":\"Sungsam Lee, Jong-Woo Park, Kwangwook Lee, S. Jang, Junhong Lee, H. Byun, Ilgweon Kim, Yongjin Choi, M.S. Shim, D. Song, Joosung Park, Tae-woo Lee, D.W. Shin, G. Jin, Kinam Kim\",\"doi\":\"10.1109/ESSDERC.2007.4430944\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.\",\"PeriodicalId\":103959,\"journal\":{\"name\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2007.4430944\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430944","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

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摘要

提出了一种利用凹槽沟道晶体管的新型有源隔离结构——横向扩展有源。通过在60 nm技术节点DRAM中实现LatEx活性，通过减少源/漏面积和提高阈下斜率(由于减少了顶部沟槽剖面和垂直底部沟槽过程的横截面积)，成功地提高了数据保留时间。本文证明了LatEx有源耦合SRCAT技术适用于60nm以下的DRAM单元阵列晶体管技术。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Lateral-Extended (LatEx.) active for improvement of data retention time for sub 60nm DRAM era

A new active isolation structure, LatEx (lateral-extended) active, which exploits recess channel transistors, is proposed. By realizing the LatEx active, data retention time enhancement was successfully achieved in 60 nm technology node DRAM by virtue of reduced source/drain area and improved subthreshold slope due to decreased cross-sectional area of top trench profile and vertical bottom trench process. In this paper, LatEx active coupled with SRCAT is proved to be suitable for sub 60 nm DRAM cell array transistor technology.

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ESSDERC 2007 - 37th European Solid State Device Research Conference

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