U. Hashim, R. Ayub, K. On, Lau Boon Leong, Y. Eric
{"title":"0.6 /spl mu/m FLOTOX EEPROM单元的编程速度表征","authors":"U. Hashim, R. Ayub, K. On, Lau Boon Leong, Y. Eric","doi":"10.1109/SMELEC.2002.1217842","DOIUrl":null,"url":null,"abstract":"Non-volatile memory processes, in particular the EEPROM process, is one the hardest process to be developed. Compared to a CMOS process, the EEPROM process has extra requirements which are high voltage transistors (>16 V), EEPROM cells, ONO layers, the buried N+ layer, thin tunnel oxide and stacked poly gates. EEPROM devices are judged on the programming speed, which relates to program high (erase) and program low (write) operations. It is essential that the program high and program low speed of the EEPROM cell is within 1 ms with a programming voltage of not more than 16 V. Two experiments were setup to improve the programming speed. The first experiment was to increase the high voltage NMOS drain junction breakdown voltage with the source floating (HVNMOS BVDSF), and the second experiment was to scale down the ONO layer. The characterization work to increase the programming speed of the memory cells of a 16 k FLOTOX EEPROM device has been carried out. P-field implant dose is optimized to have both the HVNMOS BVDSF and the p-field threshold above 16 V for fast programming. A program high threshold voltage (V/sub tH/) of 4.5 V and a program low threshold voltage (V/sub tL/) of -0.94 V are achieved.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Programming speed characterization of 0.6 /spl mu/m FLOTOX EEPROM cell\",\"authors\":\"U. Hashim, R. Ayub, K. On, Lau Boon Leong, Y. Eric\",\"doi\":\"10.1109/SMELEC.2002.1217842\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Non-volatile memory processes, in particular the EEPROM process, is one the hardest process to be developed. Compared to a CMOS process, the EEPROM process has extra requirements which are high voltage transistors (>16 V), EEPROM cells, ONO layers, the buried N+ layer, thin tunnel oxide and stacked poly gates. EEPROM devices are judged on the programming speed, which relates to program high (erase) and program low (write) operations. It is essential that the program high and program low speed of the EEPROM cell is within 1 ms with a programming voltage of not more than 16 V. Two experiments were setup to improve the programming speed. The first experiment was to increase the high voltage NMOS drain junction breakdown voltage with the source floating (HVNMOS BVDSF), and the second experiment was to scale down the ONO layer. The characterization work to increase the programming speed of the memory cells of a 16 k FLOTOX EEPROM device has been carried out. P-field implant dose is optimized to have both the HVNMOS BVDSF and the p-field threshold above 16 V for fast programming. A program high threshold voltage (V/sub tH/) of 4.5 V and a program low threshold voltage (V/sub tL/) of -0.94 V are achieved.\",\"PeriodicalId\":211819,\"journal\":{\"name\":\"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-12-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SMELEC.2002.1217842\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SMELEC.2002.1217842","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Programming speed characterization of 0.6 /spl mu/m FLOTOX EEPROM cell
Non-volatile memory processes, in particular the EEPROM process, is one the hardest process to be developed. Compared to a CMOS process, the EEPROM process has extra requirements which are high voltage transistors (>16 V), EEPROM cells, ONO layers, the buried N+ layer, thin tunnel oxide and stacked poly gates. EEPROM devices are judged on the programming speed, which relates to program high (erase) and program low (write) operations. It is essential that the program high and program low speed of the EEPROM cell is within 1 ms with a programming voltage of not more than 16 V. Two experiments were setup to improve the programming speed. The first experiment was to increase the high voltage NMOS drain junction breakdown voltage with the source floating (HVNMOS BVDSF), and the second experiment was to scale down the ONO layer. The characterization work to increase the programming speed of the memory cells of a 16 k FLOTOX EEPROM device has been carried out. P-field implant dose is optimized to have both the HVNMOS BVDSF and the p-field threshold above 16 V for fast programming. A program high threshold voltage (V/sub tH/) of 4.5 V and a program low threshold voltage (V/sub tL/) of -0.94 V are achieved.
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