ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)最新文献
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217834
H. Mun, M. Muhamad
The work concerns the study of a 980-nm strained quantum well (QW) laser diode which is suitable for pumping Er/sup 3+/ doped fiber amplifiers. The concept of a strained QW in the design of the active layer of the laser diode is reviewed. A model of 980-nm strained multiple quantum-well (MQW) with InGaAs/GaAs active medium has been simulated. The simulation results include the comparison of optical gain between the transverse electric (TE) mode and transverse magnetic (TM) mode using carrier concentration as a parameter, the role of strain in QW and the field distribution across the direction of the epitaxial growth of heterostructure. Within the spectral range of 1.20-1.40 eV (wavelength 886-1034 nm), the results are reasonable and consistent with the basic principles employed in the optical properties of quantum well lasers.
{"title":"Strained quantum well heterostructure: modeling and simulation of 980 nm","authors":"H. Mun, M. Muhamad","doi":"10.1109/SMELEC.2002.1217834","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217834","url":null,"abstract":"The work concerns the study of a 980-nm strained quantum well (QW) laser diode which is suitable for pumping Er/sup 3+/ doped fiber amplifiers. The concept of a strained QW in the design of the active layer of the laser diode is reviewed. A model of 980-nm strained multiple quantum-well (MQW) with InGaAs/GaAs active medium has been simulated. The simulation results include the comparison of optical gain between the transverse electric (TE) mode and transverse magnetic (TM) mode using carrier concentration as a parameter, the role of strain in QW and the field distribution across the direction of the epitaxial growth of heterostructure. Within the spectral range of 1.20-1.40 eV (wavelength 886-1034 nm), the results are reasonable and consistent with the basic principles employed in the optical properties of quantum well lasers.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124467202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217830
H. Roszairi, S. A. Rahman
Hydrogenated amorphous silicon thin films were prepared by d.c. plasma enhanced chemical vapour deposition (PECVD) of helium diluted silane. Gas mixtures containing different helium to silane flow-rate ratios have been used to produce these films. The films have been analysed using optical transmission spectroscopy, infrared transmission spectroscopy and X-ray diffraction. The X-ray diffraction results clearly indicate the presence of two phases in the material: microcrystalline and amorphous phase when the helium to silane flow-rate ratio was between two and four. However, further helium dilution resulted in a purely amorphous film structure as in films produced from the discharge of pure silane. The optical properties, hydrogen content and microstructure parameter of the films were obtained from the optical and infrared transmission spectra of these films. The effects of the appearance of the microcrystalline phase on these properties were also investigated.
{"title":"High deposition rate thin film hydrogenated amorphous silicon prepared by d.c. plasma enhanced chemical vapour deposition of helium diluted silane","authors":"H. Roszairi, S. A. Rahman","doi":"10.1109/SMELEC.2002.1217830","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217830","url":null,"abstract":"Hydrogenated amorphous silicon thin films were prepared by d.c. plasma enhanced chemical vapour deposition (PECVD) of helium diluted silane. Gas mixtures containing different helium to silane flow-rate ratios have been used to produce these films. The films have been analysed using optical transmission spectroscopy, infrared transmission spectroscopy and X-ray diffraction. The X-ray diffraction results clearly indicate the presence of two phases in the material: microcrystalline and amorphous phase when the helium to silane flow-rate ratio was between two and four. However, further helium dilution resulted in a purely amorphous film structure as in films produced from the discharge of pure silane. The optical properties, hydrogen content and microstructure parameter of the films were obtained from the optical and infrared transmission spectra of these films. The effects of the appearance of the microcrystalline phase on these properties were also investigated.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120878717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217803
H. Younan, K.S. Chonh, P. Shirley, S. Redkar
The work presented here shows that a significant improvement on the 155 Wright etch has been made. To completely remove the polysilicon layer on the large capacitor structure and obtain better Wright etch results, a new polysilicon etchant, HB91, has been introduced into the new procedures of 155 Wright etch. HB91 is actually a mixture solution of two chemical namely nitric acid (HNO/sub 3/) and buffer oxide etchant (BOE) in a 9:1 ration. Using it, the polysilicon layer on the large capacitor structure can be easily removed in 8-10 secs. It has been applied in failure analysis of the QBD failure in the 0.8 /spl mu/m EEPROM process in wafer fabrication. The application results showed that this new Wright etch method is more effective on checking stacking faults or silicon crystalline defects especially for those devices with large capacitor structure.
{"title":"Improvement of 155 Wright etch and its application in failure analysis of in-line QBD failure in wafer fabrication","authors":"H. Younan, K.S. Chonh, P. Shirley, S. Redkar","doi":"10.1109/SMELEC.2002.1217803","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217803","url":null,"abstract":"The work presented here shows that a significant improvement on the 155 Wright etch has been made. To completely remove the polysilicon layer on the large capacitor structure and obtain better Wright etch results, a new polysilicon etchant, HB91, has been introduced into the new procedures of 155 Wright etch. HB91 is actually a mixture solution of two chemical namely nitric acid (HNO/sub 3/) and buffer oxide etchant (BOE) in a 9:1 ration. Using it, the polysilicon layer on the large capacitor structure can be easily removed in 8-10 secs. It has been applied in failure analysis of the QBD failure in the 0.8 /spl mu/m EEPROM process in wafer fabrication. The application results showed that this new Wright etch method is more effective on checking stacking faults or silicon crystalline defects especially for those devices with large capacitor structure.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123449191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217882
L. H. Aun, A. Ihsan, M. Nor
This paper focuses on the design of acoustic microsensor using finite element analysis with multiphysics coupling. Piezoelectric materials (PZT 5A) are used as the cantilever beams for the acoustic microsensor. These cantilever beams have different lengths to sense sound signals at the range of 20 Hz to 20 kHz. When the sound signals are applied to the acoustic microsensor, the beams will vibrate at their respective resonant frequencies to produce the electrical potentials. The electrostatic computations are coupled with the structural mechanical computation via a piezo-electrical relationship. Eigen frequency solver is used to find the natural frequencies of the cantilever beams.
{"title":"Coupled structural-electrostatic analysis of acoustic microsensor","authors":"L. H. Aun, A. Ihsan, M. Nor","doi":"10.1109/SMELEC.2002.1217882","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217882","url":null,"abstract":"This paper focuses on the design of acoustic microsensor using finite element analysis with multiphysics coupling. Piezoelectric materials (PZT 5A) are used as the cantilever beams for the acoustic microsensor. These cantilever beams have different lengths to sense sound signals at the range of 20 Hz to 20 kHz. When the sound signals are applied to the acoustic microsensor, the beams will vibrate at their respective resonant frequencies to produce the electrical potentials. The electrostatic computations are coupled with the structural mechanical computation via a piezo-electrical relationship. Eigen frequency solver is used to find the natural frequencies of the cantilever beams.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123797297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217869
R. Wagiran, A.B. Chong, I. Ahmad
The work presented here shows the comparison of IC design using Tanner EDA (arithmetic logic unit) of 74382 IC using static logic gate and pass logic gate. Tanner tools are used for the schematic and layout simulation as well as the schematic versus layout comparison. The simulation technology used is Mosis 2.0 /spl mu/m.
{"title":"Pass transistor logic ALU design","authors":"R. Wagiran, A.B. Chong, I. Ahmad","doi":"10.1109/SMELEC.2002.1217869","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217869","url":null,"abstract":"The work presented here shows the comparison of IC design using Tanner EDA (arithmetic logic unit) of 74382 IC using static logic gate and pass logic gate. Tanner tools are used for the schematic and layout simulation as well as the schematic versus layout comparison. The simulation technology used is Mosis 2.0 /spl mu/m.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129885817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217844
A. Stojcevski, J. Singh, A. Zayegh
A new reconfigurable pipeline ADC has been proposed for a mobile terminal receiver that can drastically reduce power dissipation dependent on adjacent channel interference. The proposed design automatically scales the word length by monitoring the in-band and out-of-band powers. The new ADC performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. Results show that the reconfigurable architecture (ADC) can save up to of 75% power dissipation when compared to a fixed word length ADC of 16 bits. This will prolong talk and standby time in a mobile terminal.
{"title":"Scalable pipeline analog-to-digital converter for UTRA-TDD mobile station receiver","authors":"A. Stojcevski, J. Singh, A. Zayegh","doi":"10.1109/SMELEC.2002.1217844","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217844","url":null,"abstract":"A new reconfigurable pipeline ADC has been proposed for a mobile terminal receiver that can drastically reduce power dissipation dependent on adjacent channel interference. The proposed design automatically scales the word length by monitoring the in-band and out-of-band powers. The new ADC performance was evaluated in a simulation UTRA-TDD environment because of the large near far problem caused by adjacent channel interference from adjacent mobiles and base stations. Results show that the reconfigurable architecture (ADC) can save up to of 75% power dissipation when compared to a fixed word length ADC of 16 bits. This will prolong talk and standby time in a mobile terminal.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129915361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217801
H. Younan, S. Redkar, Lau Chi-Kwan, L. Jianhua
So far, it is difficult to determine quantitatively very lower level fluorine in packaging materials in wafer fabrication. In this paper, we will introduce a rapid determination technique, Ion Chromatography, to determine trace of fluorine in packaging foam materials. Using this method, the concentration of fluorine in packaging foam materials can be quantitatively determined very lower level (<4 ng/cm/sup 2/). The advantages of this method are fast, accurate and repeatable of the results obtained. In this paper, we will introduce this determination method and discuss the details of sample preparation, determination conditions and results.
{"title":"Ion chromatography analysis of fluorine contamination in wafer packaging materials","authors":"H. Younan, S. Redkar, Lau Chi-Kwan, L. Jianhua","doi":"10.1109/SMELEC.2002.1217801","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217801","url":null,"abstract":"So far, it is difficult to determine quantitatively very lower level fluorine in packaging materials in wafer fabrication. In this paper, we will introduce a rapid determination technique, Ion Chromatography, to determine trace of fluorine in packaging foam materials. Using this method, the concentration of fluorine in packaging foam materials can be quantitatively determined very lower level (<4 ng/cm/sup 2/). The advantages of this method are fast, accurate and repeatable of the results obtained. In this paper, we will introduce this determination method and discuss the details of sample preparation, determination conditions and results.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114094829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217815
S. Khucharoensin, V. Kasemsuwan
This paper presents a 3VoIt high frequency and low input impedance CMOS current mode precision full-wave rectifier. The circuit is designed based on an improved Wilson current miller. All MOS transistors are biased at low current resulting in small power dissipation. Negative feedback has been employed to reduce the input impedance of the circuit(236 /spl Omega/). HSPICE is used to perform the simulation and the result shows the frequency of operation as high as 100 MHz with a standard 0.5 /spl mu/m CMOS technology. The mismatch obtained from the input and rectifier's output is 0.21% for an input current of /spl plusmn/150 /spl mu/A. The DC transfer characteristic shows good linearity, very sharp corner at zero crossing point and good symmetry during positive and negative input cycle while power dissipation is 5.8 /spl mu/W.
{"title":"A 3Volt high frequency and low input impedance CMOS current-mode precision full-wave rectifier","authors":"S. Khucharoensin, V. Kasemsuwan","doi":"10.1109/SMELEC.2002.1217815","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217815","url":null,"abstract":"This paper presents a 3VoIt high frequency and low input impedance CMOS current mode precision full-wave rectifier. The circuit is designed based on an improved Wilson current miller. All MOS transistors are biased at low current resulting in small power dissipation. Negative feedback has been employed to reduce the input impedance of the circuit(236 /spl Omega/). HSPICE is used to perform the simulation and the result shows the frequency of operation as high as 100 MHz with a standard 0.5 /spl mu/m CMOS technology. The mismatch obtained from the input and rectifier's output is 0.21% for an input current of /spl plusmn/150 /spl mu/A. The DC transfer characteristic shows good linearity, very sharp corner at zero crossing point and good symmetry during positive and negative input cycle while power dissipation is 5.8 /spl mu/W.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121651511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217855
K. John
This paper discuss on how to develop a hard real-time machine control system with Microsoft Windows NT Operating System, where the respond must be within 0.5 milliseconds. The attempt to use a general-purpose operating system (Microsoft Windows NT 4.0 Workstation) is because there is abundance of Commercial-Off-the-Shelf Components (COTS), easily available tools (compilers, and 3 party tools) and need not to learn another operating system behavior. The most important factor is there is no single dominant operating system or tools vendor for real-time operating system. Since the no single dominant real-time operating system development under real-time operating system is riskier and more costly. Ideally codes must be portable between different operating system where it is apparent with Windows platforms, Windows 95/98, Windows ME, Windows 2000, Windows XP or even Windows CE. Firstly study was done on how Microsoft Windows NT operating system works internally from materials from Microsoft Software Development Network (MSDN). Secondly study was done how to take advantage of the operating system to create a real time application. Microsoft Windows NT is a general purpose operating system that does not support real time application development, but it has all the vital elements that a real time operating system needs. The vital elements are priority-driven, preemptive scheduler, preemptive interrupt handler (for critical interrupts), deferred procedure calls (DPC) for non-critical (DPC executes after ISR), synchronization and deterministic response time. With these vital elements and some modification to application codes to enable it to execute in higher priority level, would result a real time application. This does not mean changing all the codes to higher priority is the solution, as it would cause system to malfunction as other device driver or low-level interface run at high priority too and this would lock up the system. With the combination of priority level, synchronization a complete real time solution can be implemented and this paper covers the concept. This concept also explains what was done to overcome the need of special hardware (as recommended) to accomplish hard real-time application with the response of 0.5 milliseconds.
本文讨论了如何在Microsoft Windows NT操作系统下开发一个响应时间必须在0.5毫秒以内的硬实时机床控制系统。尝试使用通用操作系统(Microsoft Windows NT 4.0工作站)是因为有大量的商用现成组件(COTS)，容易获得的工具(编译器和三方工具)，并且不需要学习其他操作系统的行为。最重要的因素是，实时操作系统没有单一的主导操作系统或工具供应商。由于没有单一的占主导地位的实时操作系统，在实时操作系统下开发风险更大，成本更高。理想情况下，代码必须在不同的操作系统之间可移植，这在Windows平台、Windows 95/98、Windows ME、Windows 2000、Windows XP甚至Windows CE上都很明显。首先利用微软软件开发网络(MSDN)的资料对微软Windows NT操作系统的内部工作原理进行了研究。其次，研究了如何利用操作系统的优势创建实时应用程序。Microsoft Windows NT是一个通用的操作系统，它不支持实时应用程序开发，但它具有实时操作系统所需的所有重要元素。关键要素是优先级驱动、抢占式调度器、抢占式中断处理程序(用于关键中断)、用于非关键中断的延迟过程调用(DPC在ISR之后执行)、同步和确定性响应时间。有了这些重要元素，再对应用程序代码进行一些修改，使其能够在更高的优先级级别上执行，就会产生一个实时应用程序。这并不意味着将所有代码更改为更高优先级是解决方案，因为它会导致系统故障，因为其他设备驱动程序或低级接口也以高优先级运行，这将锁定系统。结合优先级，可以实现完整的实时同步解决方案，本文介绍了这一概念。这个概念还解释了如何克服对特殊硬件(按照建议)的需求，以实现响应为0.5毫秒的硬实时应用程序。
{"title":"Control system development for test handler","authors":"K. John","doi":"10.1109/SMELEC.2002.1217855","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217855","url":null,"abstract":"This paper discuss on how to develop a hard real-time machine control system with Microsoft Windows NT Operating System, where the respond must be within 0.5 milliseconds. The attempt to use a general-purpose operating system (Microsoft Windows NT 4.0 Workstation) is because there is abundance of Commercial-Off-the-Shelf Components (COTS), easily available tools (compilers, and 3 party tools) and need not to learn another operating system behavior. The most important factor is there is no single dominant operating system or tools vendor for real-time operating system. Since the no single dominant real-time operating system development under real-time operating system is riskier and more costly. Ideally codes must be portable between different operating system where it is apparent with Windows platforms, Windows 95/98, Windows ME, Windows 2000, Windows XP or even Windows CE. Firstly study was done on how Microsoft Windows NT operating system works internally from materials from Microsoft Software Development Network (MSDN). Secondly study was done how to take advantage of the operating system to create a real time application. Microsoft Windows NT is a general purpose operating system that does not support real time application development, but it has all the vital elements that a real time operating system needs. The vital elements are priority-driven, preemptive scheduler, preemptive interrupt handler (for critical interrupts), deferred procedure calls (DPC) for non-critical (DPC executes after ISR), synchronization and deterministic response time. With these vital elements and some modification to application codes to enable it to execute in higher priority level, would result a real time application. This does not mean changing all the codes to higher priority is the solution, as it would cause system to malfunction as other device driver or low-level interface run at high priority too and this would lock up the system. With the combination of priority level, synchronization a complete real time solution can be implemented and this paper covers the concept. This concept also explains what was done to overcome the need of special hardware (as recommended) to accomplish hard real-time application with the response of 0.5 milliseconds.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124229743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-12-19DOI: 10.1109/SMELEC.2002.1217842
U. Hashim, R. Ayub, K. On, Lau Boon Leong, Y. Eric
Non-volatile memory processes, in particular the EEPROM process, is one the hardest process to be developed. Compared to a CMOS process, the EEPROM process has extra requirements which are high voltage transistors (>16 V), EEPROM cells, ONO layers, the buried N+ layer, thin tunnel oxide and stacked poly gates. EEPROM devices are judged on the programming speed, which relates to program high (erase) and program low (write) operations. It is essential that the program high and program low speed of the EEPROM cell is within 1 ms with a programming voltage of not more than 16 V. Two experiments were setup to improve the programming speed. The first experiment was to increase the high voltage NMOS drain junction breakdown voltage with the source floating (HVNMOS BVDSF), and the second experiment was to scale down the ONO layer. The characterization work to increase the programming speed of the memory cells of a 16 k FLOTOX EEPROM device has been carried out. P-field implant dose is optimized to have both the HVNMOS BVDSF and the p-field threshold above 16 V for fast programming. A program high threshold voltage (V/sub tH/) of 4.5 V and a program low threshold voltage (V/sub tL/) of -0.94 V are achieved.
{"title":"Programming speed characterization of 0.6 /spl mu/m FLOTOX EEPROM cell","authors":"U. Hashim, R. Ayub, K. On, Lau Boon Leong, Y. Eric","doi":"10.1109/SMELEC.2002.1217842","DOIUrl":"https://doi.org/10.1109/SMELEC.2002.1217842","url":null,"abstract":"Non-volatile memory processes, in particular the EEPROM process, is one the hardest process to be developed. Compared to a CMOS process, the EEPROM process has extra requirements which are high voltage transistors (>16 V), EEPROM cells, ONO layers, the buried N+ layer, thin tunnel oxide and stacked poly gates. EEPROM devices are judged on the programming speed, which relates to program high (erase) and program low (write) operations. It is essential that the program high and program low speed of the EEPROM cell is within 1 ms with a programming voltage of not more than 16 V. Two experiments were setup to improve the programming speed. The first experiment was to increase the high voltage NMOS drain junction breakdown voltage with the source floating (HVNMOS BVDSF), and the second experiment was to scale down the ONO layer. The characterization work to increase the programming speed of the memory cells of a 16 k FLOTOX EEPROM device has been carried out. P-field implant dose is optimized to have both the HVNMOS BVDSF and the p-field threshold above 16 V for fast programming. A program high threshold voltage (V/sub tH/) of 4.5 V and a program low threshold voltage (V/sub tL/) of -0.94 V are achieved.","PeriodicalId":211819,"journal":{"name":"ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2002-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126504193","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
ICONIP '02. Proceedings of the 9th International Conference on Neural Information Processing. Computational Intelligence for the E-Age (IEEE Cat. No.02EX575)
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