具有无程序冗余的7 ns 1 Mb BiCMOS ECL SRAM

Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI:10.1109/VLSIC.1990.111085

A. Ohba, S. Ohbayashi, T. Shiomi, S. Takano, K. Anami, H. Honda, Y. Ishigaki, M. Hatanaka, S. Nagao, S. Kayano

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引用次数: 7

摘要

描述了具有无程序冗余的7-ns, 1 M×1/256 K×4 BiCMOS ECL(发射极耦合逻辑)SRAM。为了获得更快的地址访问时间和更低的功耗，采用了改进的ECL缓冲器和两级感知方案。SRAM采用0.8- m双多晶硅双金属BiCMOS技术制备。RAM具有ECL 10 K接口，并在-5.2 V的电源电压下工作。访问时间为7ns。有效值680mw，适用于4次模式。细胞大小为5.4 μ m × 7.2 μ m (38.88 μ m²);模具尺寸为5.46 mm × 16.16 mm (88.24 mm2)

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A 7 ns 1 Mb BiCMOS ECL SRAM with program-free redundancy

A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a supply voltage of -5.2 V. An access time of 7 ns has been obtained. Active 680 mW for ×4 mode. The cell size is 5.4 μm×7.2 μm (38.88 μm2); the die size is 5.46 mm×16.16 mm (88.24 mm2)

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Digest of Technical Papers., 1990 Symposium on VLSI Circuits

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