{"title":"采用混合信号反馈环路的数字PWM和数字环路滤波器的d类放大器","authors":"M. Auer, Timuçin Karaca","doi":"10.1109/ESSCIRC.2019.8902785","DOIUrl":null,"url":null,"abstract":"A digital class-D audio amplifier is presented that is based on digital pulse-width modulation (PWM) and a combination of digital and analog feedback. Unlike other recent implementations for low-power applications this amplifier directly accepts digital input as the digital-to-analog conversion is an inherent feature of the presented topology.The feedback topology uses a hybrid scheme with digital feedback to improve the performance of the PWM and analog-feedback to mitigate analog imperfections and to improve power supply rejection. Because of the proposed feedback scheme, the requirements on the analog-to-digital converter (ADC) in the feedback loop are greatly relaxed allowing the use of a continuous-time ∆Σ-modulator with low power consumption.The class-D amplifier was realized in a standard 180 nm CMOS technologies and drives 1.2 W into an 8 Ω load and achieves a total harmonic distortion plus noise (THD+N) of −96 dB, a signal-to-noise ratio (SNR) of 99.9 dB having an efficiency of 91 %.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop\",\"authors\":\"M. Auer, Timuçin Karaca\",\"doi\":\"10.1109/ESSCIRC.2019.8902785\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A digital class-D audio amplifier is presented that is based on digital pulse-width modulation (PWM) and a combination of digital and analog feedback. Unlike other recent implementations for low-power applications this amplifier directly accepts digital input as the digital-to-analog conversion is an inherent feature of the presented topology.The feedback topology uses a hybrid scheme with digital feedback to improve the performance of the PWM and analog-feedback to mitigate analog imperfections and to improve power supply rejection. Because of the proposed feedback scheme, the requirements on the analog-to-digital converter (ADC) in the feedback loop are greatly relaxed allowing the use of a continuous-time ∆Σ-modulator with low power consumption.The class-D amplifier was realized in a standard 180 nm CMOS technologies and drives 1.2 W into an 8 Ω load and achieves a total harmonic distortion plus noise (THD+N) of −96 dB, a signal-to-noise ratio (SNR) of 99.9 dB having an efficiency of 91 %.\",\"PeriodicalId\":402948,\"journal\":{\"name\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2019.8902785\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Class-D Amplifier with Digital PWM and Digital Loop-Filter using a Mixed-Signal Feedback Loop
A digital class-D audio amplifier is presented that is based on digital pulse-width modulation (PWM) and a combination of digital and analog feedback. Unlike other recent implementations for low-power applications this amplifier directly accepts digital input as the digital-to-analog conversion is an inherent feature of the presented topology.The feedback topology uses a hybrid scheme with digital feedback to improve the performance of the PWM and analog-feedback to mitigate analog imperfections and to improve power supply rejection. Because of the proposed feedback scheme, the requirements on the analog-to-digital converter (ADC) in the feedback loop are greatly relaxed allowing the use of a continuous-time ∆Σ-modulator with low power consumption.The class-D amplifier was realized in a standard 180 nm CMOS technologies and drives 1.2 W into an 8 Ω load and achieves a total harmonic distortion plus noise (THD+N) of −96 dB, a signal-to-noise ratio (SNR) of 99.9 dB having an efficiency of 91 %.