Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya
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A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS
A low voltage buck DC-DC converter (0.45-V input, 0.4-V output) with on-chip gate boosted (OGB) and clock frequency scaled digital PWM controller is designed in 40-nm CMOS process. The highest efficiency to date is achieved at the output power less than 40μW. In order to compensate for the die-to-die delay variations of a delay line in the proposed digital PWM controller, a linear delay trimming by a logarithmic stress voltage (LSV) scheme with good controllability is also proposed and verified in measurement.
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