一个500 MS/s的10位单通道SAR ADC，带双速率比较器

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2019-09-01 DOI:10.1109/ESSCIRC.2019.8902706

Q. Fan, Runxi Zhang, P. Bikkina, E. Mikkola, Jinghong Chen

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引用次数: 1

摘要

本文提出了一种500 MS/s的10位单通道SAR ADC，该ADC具有可重构的双速率比较器，以提高运算速度。所提出的双速率比较器有效地消除了由比较器从关键路径复位引起的延迟，同时功耗更低，时钟频率降低一半。采用28纳米FDSOI工艺制作了测试芯片。该ADC的时钟频率为500 MS/s，在Nyquist上实现了52.7 dB的SNDR和62.49 dB的SFDR，功耗为1.18 mW, Walden FOM为6.7 fJ/ v. step。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

This paper presents a 500 MS/s 10-bit single-channel SAR ADC with a reconfigurable double-rate comparator for enhanced operation speed. The proposed double-rate comparator effectively eliminates the delay caused by comparator reset from the critical path while consuming less power and reducing the clock frequency by half. A test chip is fabricated in a 28 nm FDSOI technology. Clocked at 500 MS/s, the proposed ADC achieves a SNDR of 52.7 dB and a SFDR of 62.49 dB at Nyquist with a power consumption of 1.18 mW, showing a Walden FOM of 6.7 fJ/conv.-step.

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ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)

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