{"title":"光电多芯片模块的划分","authors":"J. Fan, B. Catanzaro, C.K. Cheng, S.H. Lee","doi":"10.1109/MCMC.1994.292513","DOIUrl":null,"url":null,"abstract":"This paper is the first attempt at using CAD for partitioning opto-electronic systems into opto-electronic multichip modules (OE MCM). We define a formulation for OE MCM partitioning and describe a new algorithm for optimizing this partitioning based on the minimization of the power consumption. We have implemented the algorithm by applying it to a multistage interconnect network and analyzing the improvement of the design.<<ETX>>","PeriodicalId":292463,"journal":{"name":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Partitioning of opto-electronic multichip modules\",\"authors\":\"J. Fan, B. Catanzaro, C.K. Cheng, S.H. Lee\",\"doi\":\"10.1109/MCMC.1994.292513\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper is the first attempt at using CAD for partitioning opto-electronic systems into opto-electronic multichip modules (OE MCM). We define a formulation for OE MCM partitioning and describe a new algorithm for optimizing this partitioning based on the minimization of the power consumption. We have implemented the algorithm by applying it to a multistage interconnect network and analyzing the improvement of the design.<<ETX>>\",\"PeriodicalId\":292463,\"journal\":{\"name\":\"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-03-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1994.292513\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE Multi-Chip Module Conference (MCMC-94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1994.292513","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper is the first attempt at using CAD for partitioning opto-electronic systems into opto-electronic multichip modules (OE MCM). We define a formulation for OE MCM partitioning and describe a new algorithm for optimizing this partitioning based on the minimization of the power consumption. We have implemented the algorithm by applying it to a multistage interconnect network and analyzing the improvement of the design.<>