Dependence of dielectric time to breakdown distributions on test structure area

Problems arising from the use of a test structure area that is too small or too large when performing dielectric reliability investigations of DRAMs (dynamic random-access memories) are pointed out. The authors discuss the applicability of different models for the transformation of measured t/sub bd/ distributions to larger areas and demonstrate the feasibility of the mathematical combination of subareas within the same chip to a larger area. An optimum test structure for dielectric reliability engineering for the phase of technology development is deduced.<>