一种嵌入式ECC的速度增强DRAM阵列架构

Symposium 1989 on VLSI Circuits Pub Date : 1989-05-25 DOI:10.1109/VLSIC.1989.1037514

K. Arimoto, Y. Matsuda, K. Furutani, M. Tsukude, T. Oisiii, K. Mashiko, K. Fujishima

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引用次数: 1

摘要

提出了一种新的阵列结构，并提出了相应的对策，以解决因缩比而导致的信号电荷减小的问题。在一种新的存取模型的基础上，分层数据总线配置和多用途寄存器(MPR)的结合提供了高速阵列存取。MPR还包括一个实用的阵列嵌入式ECC，在页面模式下具有很小的面积损失和没有访问开销。该阵列架构应用于按比例缩小的16mbit DRAM，实现了高性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A speed enhancement DRAM array architecture with embedded ECC

A new array architecture with countermeasures for the smaller signal charge caused by scaling down is proposed. On the basis of a new access model, the combination of a hierarchical data bus configuration and multipurpose register (MPR) provides high-speed array access. The MPR also includes a practical array-embedded ECC with little area penalty and no access overhead in the page mode. This array architecture is applied to a scaled-down 16-Mbit DRAM and has achieved high performance.

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Symposium 1989 on VLSI Circuits

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