{"title":"用于65nm CMOS时钟生成的宽频率范围分数n合成器","authors":"Ye Zhang, N. Zimmermann, R. Wunderlich, S. Heinen","doi":"10.1109/ICECS.2011.6122339","DOIUrl":null,"url":null,"abstract":"In this paper, a ring oscillator based fractional-N frequency synthesizer whose output frequency ranges from 600 MHz to 1.2 GHz is proposed. ΣΔ modulation is implemented to randomize the fractional spurs. The issues regarding a wide output frequency range are analyzed, and solved by the compensation and adaptive controlled architecture. Power and area optimization is also considered. The synthesizer was implemented in 65 nm CMOS. At 1 GHz output frequency, a phase noise performance of −107 dBc/Hz at 1 MHz offset and 5.3 ps rms jitter are achieved.","PeriodicalId":251525,"journal":{"name":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","volume":"125 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A wide-frequency-range fractional-N synthesizer for clock generation in 65nm CMOS\",\"authors\":\"Ye Zhang, N. Zimmermann, R. Wunderlich, S. Heinen\",\"doi\":\"10.1109/ICECS.2011.6122339\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a ring oscillator based fractional-N frequency synthesizer whose output frequency ranges from 600 MHz to 1.2 GHz is proposed. ΣΔ modulation is implemented to randomize the fractional spurs. The issues regarding a wide output frequency range are analyzed, and solved by the compensation and adaptive controlled architecture. Power and area optimization is also considered. The synthesizer was implemented in 65 nm CMOS. At 1 GHz output frequency, a phase noise performance of −107 dBc/Hz at 1 MHz offset and 5.3 ps rms jitter are achieved.\",\"PeriodicalId\":251525,\"journal\":{\"name\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"volume\":\"125 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 18th IEEE International Conference on Electronics, Circuits, and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICECS.2011.6122339\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 18th IEEE International Conference on Electronics, Circuits, and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICECS.2011.6122339","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A wide-frequency-range fractional-N synthesizer for clock generation in 65nm CMOS
In this paper, a ring oscillator based fractional-N frequency synthesizer whose output frequency ranges from 600 MHz to 1.2 GHz is proposed. ΣΔ modulation is implemented to randomize the fractional spurs. The issues regarding a wide output frequency range are analyzed, and solved by the compensation and adaptive controlled architecture. Power and area optimization is also considered. The synthesizer was implemented in 65 nm CMOS. At 1 GHz output frequency, a phase noise performance of −107 dBc/Hz at 1 MHz offset and 5.3 ps rms jitter are achieved.
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