选择性W-CVD和聚酰亚胺硅氧烷膜的多级金金属化研究

Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference Pub Date : 1989-06-12 DOI:10.1109/VMIC.1989.78073

K. Mikagi, T. Homma, T. Katoh, K. Tsunenari, Y. Murao

{"title":"选择性W-CVD和聚酰亚胺硅氧烷膜的多级金金属化研究","authors":"K. Mikagi, T. Homma, T. Katoh, K. Tsunenari, Y. Murao","doi":"10.1109/VMIC.1989.78073","DOIUrl":null,"url":null,"abstract":"Multilevel gold (Au) metallization was realized for high-speed VLSI devices by a novel combination of selective tungsten CVD (W-CVD) with electroplated Au and a polyimide siloxane (PSI) film developed by the authors. Selective W-CVD was applied to overcome the problem of poor adhesion between Au wiring and PSI film as well as to fill vias. Silane (SiH/sub 4/) reduced selective W-CVD application to Au wiring and an organic dielectric film (PSI) for VLSI devices have been demonstrated for the first time.<<ETX>>","PeriodicalId":302853,"journal":{"name":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Multilevel gold metallization by use of selective W-CVD and polyimide siloxane film\",\"authors\":\"K. Mikagi, T. Homma, T. Katoh, K. Tsunenari, Y. Murao\",\"doi\":\"10.1109/VMIC.1989.78073\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Multilevel gold (Au) metallization was realized for high-speed VLSI devices by a novel combination of selective tungsten CVD (W-CVD) with electroplated Au and a polyimide siloxane (PSI) film developed by the authors. Selective W-CVD was applied to overcome the problem of poor adhesion between Au wiring and PSI film as well as to fill vias. Silane (SiH/sub 4/) reduced selective W-CVD application to Au wiring and an organic dielectric film (PSI) for VLSI devices have been demonstrated for the first time.<<ETX>>\",\"PeriodicalId\":302853,\"journal\":{\"name\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VMIC.1989.78073\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VMIC.1989.78073","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

采用选择性钨CVD (W-CVD)与电镀Au和聚酰亚胺硅氧烷(PSI)膜的新组合，实现了高速VLSI器件的多级金(Au)金属化。采用选择性W-CVD技术，克服了Au线与PSI膜之间粘附不良的问题，并填补了过孔。硅烷(SiH/sub 4/)降低选择性W-CVD应用于Au布线和VLSI器件的有机介电膜(PSI)首次得到证实

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Multilevel gold metallization by use of selective W-CVD and polyimide siloxane film

Multilevel gold (Au) metallization was realized for high-speed VLSI devices by a novel combination of selective tungsten CVD (W-CVD) with electroplated Au and a polyimide siloxane (PSI) film developed by the authors. Selective W-CVD was applied to overcome the problem of poor adhesion between Au wiring and PSI film as well as to fill vias. Silane (SiH/sub 4/) reduced selective W-CVD application to Au wiring and an organic dielectric film (PSI) for VLSI devices have been demonstrated for the first time.<>

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Proceedings., Sixth International IEEE VLSI Multilevel Interconnection Conference

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