Improvement of HCI and HTRB Reliability on 100V pLDMOS for 48V Battery Applications

In this paper, improvement of gate oxide breakdown and BVdss walk-in after HCI stress of 100V PLDMOS devices was studied. The poly field plate extension applied at 60V or lower in the previous study could improve gate oxide breakdown by HCI of 100V PLDMOS. However, BVdss walk-in occurred after on-stress due to a change in the electric field distribution by changing the poly field plate. Changes in electrical potential and impact ionization were confirmed through TCAD simulation and improvements in HCI and HTRB of 100V PLDMOS devices were achieved by changing the metal field plates and N-type sinker design, in addition to poly field plates. Based on these results, we propose a novel structure for 100V class PLDMOS.