{"title":"基于dll的甚高频DVB-H/T接收机频率合成器","authors":"M. Gholami, M. Sharifkhani, S. Saeedi, M. Atarodi","doi":"10.1109/SM2ACD.2010.5672343","DOIUrl":null,"url":null,"abstract":"This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions.","PeriodicalId":442381,"journal":{"name":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A DLL-based frequency synthesizer for VHF DVB-H/T receivers\",\"authors\":\"M. Gholami, M. Sharifkhani, S. Saeedi, M. Atarodi\",\"doi\":\"10.1109/SM2ACD.2010.5672343\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions.\",\"PeriodicalId\":442381,\"journal\":{\"name\":\"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SM2ACD.2010.5672343\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 XIth International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design (SM2ACD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SM2ACD.2010.5672343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A DLL-based frequency synthesizer for VHF DVB-H/T receivers
This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions.