{"title":"在ATE上的多位点和多探针基板测试","authors":"Xiaojun Ma, F. Lombardi","doi":"10.1109/DFT.2006.45","DOIUrl":null,"url":null,"abstract":"This paper presents a novel method that utilizes multi-site and multi-probe facilities in an ATE for substrate testing. The test time for a batch can be considerably reduced by efficiently utilizing an ATE with a number of flying-probes and multiple substrates under test (SUTs). An analytical model that predicts very accurately the batch test time is proposed. This model establishes the optimal multi-site configuration as corresponding to the batch size that allow multiple SUTs to be simultaneously tested on a ATE. Simulation results for an ATE with 12 flying-probe as example of a commercially available tester are provided; for this ATE the proposed method achieves a reduction of 54.66% in test time over a single-site method (at complete coverage of the modeled faults)","PeriodicalId":113870,"journal":{"name":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-10-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Multi-Site and Multi-Probe Substrate Testing on an ATE\",\"authors\":\"Xiaojun Ma, F. Lombardi\",\"doi\":\"10.1109/DFT.2006.45\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel method that utilizes multi-site and multi-probe facilities in an ATE for substrate testing. The test time for a batch can be considerably reduced by efficiently utilizing an ATE with a number of flying-probes and multiple substrates under test (SUTs). An analytical model that predicts very accurately the batch test time is proposed. This model establishes the optimal multi-site configuration as corresponding to the batch size that allow multiple SUTs to be simultaneously tested on a ATE. Simulation results for an ATE with 12 flying-probe as example of a commercially available tester are provided; for this ATE the proposed method achieves a reduction of 54.66% in test time over a single-site method (at complete coverage of the modeled faults)\",\"PeriodicalId\":113870,\"journal\":{\"name\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-10-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DFT.2006.45\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2006.45","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multi-Site and Multi-Probe Substrate Testing on an ATE
This paper presents a novel method that utilizes multi-site and multi-probe facilities in an ATE for substrate testing. The test time for a batch can be considerably reduced by efficiently utilizing an ATE with a number of flying-probes and multiple substrates under test (SUTs). An analytical model that predicts very accurately the batch test time is proposed. This model establishes the optimal multi-site configuration as corresponding to the batch size that allow multiple SUTs to be simultaneously tested on a ATE. Simulation results for an ATE with 12 flying-probe as example of a commercially available tester are provided; for this ATE the proposed method achieves a reduction of 54.66% in test time over a single-site method (at complete coverage of the modeled faults)