{"title":"3D集成电路:实现完全集成、密集和高效电源的机会","authors":"G. Pillonnet, Nicolas Jeanniot, P. Vivet","doi":"10.1109/3DIC.2015.7334574","DOIUrl":null,"url":null,"abstract":"With 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm2 silicon area. An additional high density capacitance layer (100nF/mm2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies.","PeriodicalId":253726,"journal":{"name":"2015 International 3D Systems Integration Conference (3DIC)","volume":"716 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"3D ICs: An opportunity for fully-integrated, dense and efficient power supplies\",\"authors\":\"G. Pillonnet, Nicolas Jeanniot, P. Vivet\",\"doi\":\"10.1109/3DIC.2015.7334574\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm2 silicon area. An additional high density capacitance layer (100nF/mm2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies.\",\"PeriodicalId\":253726,\"journal\":{\"name\":\"2015 International 3D Systems Integration Conference (3DIC)\",\"volume\":\"716 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 International 3D Systems Integration Conference (3DIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/3DIC.2015.7334574\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC.2015.7334574","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
3D ICs: An opportunity for fully-integrated, dense and efficient power supplies
With 3D technologies, the in-package solution allows integrated, efficient and granular power supplies to be designed for multi-core processors. As the converter design obtains few benefits from the scaling, 3DIC allows the best technology to be chosen i.e. one which suits the DC-DC converter design. This paper evaluates the achievable power efficiency between on-die and in-package converters using a combination of active (28 and 65nm CMOS nodes) and passive (poly, MIM, vertical capacitor) layers. Based on the same load power consumption, on-die and in-package switched capacitor converters achieve 65% and 78% efficiency, respectively, in a 1mm2 silicon area. An additional high density capacitance layer (100nF/mm2) improves efficiency by more than 20 points in 65nm for the same surface which emphasizes the need for dedicated technology for better power management integration. This paper shows that in-package power management is a key alternative for fully-integrated, dense and efficient power supplies.