V. Friedman, J. Khoury, L. J. Loporcaro, M. Theobald, E. Fields, M. Tompsett, V. Gopal, G. L. Lustro, M. Figueroa
{"title":"带有片上数字回波消除器的编解码器","authors":"V. Friedman, J. Khoury, L. J. Loporcaro, M. Theobald, E. Fields, M. Tompsett, V. Gopal, G. L. Lustro, M. Figueroa","doi":"10.1109/CICC.1989.56770","DOIUrl":null,"url":null,"abstract":"A 1.5-μm CMOS codec, using Σ-Δ conversion techniques, which incorporates the hybrid echo cancellation on chip, is described. The echo cancellation is done in two states, using an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter. The limiting effects of the variation of the analog components on the echo cancellation performance of the device are minimized, so that only one set of coefficients per national standard is necessary","PeriodicalId":165054,"journal":{"name":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","volume":"195 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A codec with on-chip digital echo canceller\",\"authors\":\"V. Friedman, J. Khoury, L. J. Loporcaro, M. Theobald, E. Fields, M. Tompsett, V. Gopal, G. L. Lustro, M. Figueroa\",\"doi\":\"10.1109/CICC.1989.56770\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.5-μm CMOS codec, using Σ-Δ conversion techniques, which incorporates the hybrid echo cancellation on chip, is described. The echo cancellation is done in two states, using an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter. The limiting effects of the variation of the analog components on the echo cancellation performance of the device are minimized, so that only one set of coefficients per national standard is necessary\",\"PeriodicalId\":165054,\"journal\":{\"name\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"volume\":\"195 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1989 Proceedings of the IEEE Custom Integrated Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.1989.56770\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1989 Proceedings of the IEEE Custom Integrated Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.1989.56770","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.5-μm CMOS codec, using Σ-Δ conversion techniques, which incorporates the hybrid echo cancellation on chip, is described. The echo cancellation is done in two states, using an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter. The limiting effects of the variation of the analog components on the echo cancellation performance of the device are minimized, so that only one set of coefficients per national standard is necessary
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