{"title":"耐PVT LC-VCO的90纳米CMOS技术,用于GPS/伽利略应用","authors":"Krzysztof Siwiec, T. Borejko, W. Pleskacz","doi":"10.1109/DDECS.2011.5783042","DOIUrl":null,"url":null,"abstract":"In this paper low-voltage LC voltage-controlled oscillator (VCO) with low sensitivity to process, voltage and temperature (PVT) variations has been presented. VCO operates at 3.2 GHz and its output signal frequency is divided by 2 in quadrature divider to generate quadrature signals at 1.6 GHz. The NMOS cross-coupled architecture, proper varactor biasing, tuning curve linearization technique and switched-capacitor (SC) current source were used to reduce the sensitivity to PVT variations. The LC-VCO was designed with the usage of Low-Leakage UMC 90 nm CMOS technology. It achieves phase noise of −117 dBc/Hz at 1 MHz offset and draws 1.2 mA (VCO+Quadrature Divider) from 1.2 V supply voltage.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications\",\"authors\":\"Krzysztof Siwiec, T. Borejko, W. Pleskacz\",\"doi\":\"10.1109/DDECS.2011.5783042\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper low-voltage LC voltage-controlled oscillator (VCO) with low sensitivity to process, voltage and temperature (PVT) variations has been presented. VCO operates at 3.2 GHz and its output signal frequency is divided by 2 in quadrature divider to generate quadrature signals at 1.6 GHz. The NMOS cross-coupled architecture, proper varactor biasing, tuning curve linearization technique and switched-capacitor (SC) current source were used to reduce the sensitivity to PVT variations. The LC-VCO was designed with the usage of Low-Leakage UMC 90 nm CMOS technology. It achieves phase noise of −117 dBc/Hz at 1 MHz offset and draws 1.2 mA (VCO+Quadrature Divider) from 1.2 V supply voltage.\",\"PeriodicalId\":231389,\"journal\":{\"name\":\"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2011.5783042\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2011.5783042","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
摘要
本文提出了一种对工艺、电压和温度(PVT)变化低灵敏度的低压LC压控振荡器(VCO)。VCO工作在3.2 GHz,其输出信号频率在正交分频器中除以2,产生1.6 GHz的正交信号。采用NMOS交叉耦合结构、适当的变容偏置、调谐曲线线性化技术和开关电容(SC)电流源降低了对PVT变化的灵敏度。LC-VCO采用低泄漏UMC 90纳米CMOS技术设计。它在1 MHz偏置时实现了- 117 dBc/Hz的相位噪声,并从1.2 V电源电压中提取1.2 mA (VCO+正交分频器)。
PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications
In this paper low-voltage LC voltage-controlled oscillator (VCO) with low sensitivity to process, voltage and temperature (PVT) variations has been presented. VCO operates at 3.2 GHz and its output signal frequency is divided by 2 in quadrature divider to generate quadrature signals at 1.6 GHz. The NMOS cross-coupled architecture, proper varactor biasing, tuning curve linearization technique and switched-capacitor (SC) current source were used to reduce the sensitivity to PVT variations. The LC-VCO was designed with the usage of Low-Leakage UMC 90 nm CMOS technology. It achieves phase noise of −117 dBc/Hz at 1 MHz offset and draws 1.2 mA (VCO+Quadrature Divider) from 1.2 V supply voltage.