{"title":"1-GS/s 8位12.01-fJ/转换器。采用28纳米FDSOI技术的两步SAR ADC","authors":"Q. Fan, Jinghong Chen","doi":"10.1109/ESSCIRC.2019.8902925","DOIUrl":null,"url":null,"abstract":"This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of the conversion rate. A modified StrongARM latch is adopted to further reduce the comparator noise. A calibration procedure runs in the background to address the nonuniform comparator offsets and the interstage gain error. Fabricated in a 28-nm FDSOI process, the prototype ADC achieves an SNDR of 46.65 dB at Nyquist with a power consumption of 2.1 mW, leading into a Walden FOM of 12.01 fJ/conv.-step.","PeriodicalId":402948,"journal":{"name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology\",\"authors\":\"Q. Fan, Jinghong Chen\",\"doi\":\"10.1109/ESSCIRC.2019.8902925\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of the conversion rate. A modified StrongARM latch is adopted to further reduce the comparator noise. A calibration procedure runs in the background to address the nonuniform comparator offsets and the interstage gain error. Fabricated in a 28-nm FDSOI process, the prototype ADC achieves an SNDR of 46.65 dB at Nyquist with a power consumption of 2.1 mW, leading into a Walden FOM of 12.01 fJ/conv.-step.\",\"PeriodicalId\":402948,\"journal\":{\"name\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2019.8902925\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2019.8902925","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology
This letter presents a partially interleaved 1-GS/s 8-bit two-step SAR ADC for low-power operations. A fast noise-reduction technique is proposed to increase the power efficiency without significant degradation of the conversion rate. A modified StrongARM latch is adopted to further reduce the comparator noise. A calibration procedure runs in the background to address the nonuniform comparator offsets and the interstage gain error. Fabricated in a 28-nm FDSOI process, the prototype ADC achieves an SNDR of 46.65 dB at Nyquist with a power consumption of 2.1 mW, leading into a Walden FOM of 12.01 fJ/conv.-step.
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