S. Kosonocky, A. Bright, K. W. Warren, R. Haring, S. Klepner, S. Asaad, S. Basavaiah, Bob Havreluk, D. Heidel, M. Immediato, K. Jenkins, R. Joshi, B. Parker, T. Rajeevakumar, K. Stawiasz
{"title":"在芯片上设计一个可测试的系统","authors":"S. Kosonocky, A. Bright, K. W. Warren, R. Haring, S. Klepner, S. Asaad, S. Basavaiah, Bob Havreluk, D. Heidel, M. Immediato, K. Jenkins, R. Joshi, B. Parker, T. Rajeevakumar, K. Stawiasz","doi":"10.1109/VTEST.1998.670841","DOIUrl":null,"url":null,"abstract":"A \"system on a chip\" is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Designing a testable system on a chip\",\"authors\":\"S. Kosonocky, A. Bright, K. W. Warren, R. Haring, S. Klepner, S. Asaad, S. Basavaiah, Bob Havreluk, D. Heidel, M. Immediato, K. Jenkins, R. Joshi, B. Parker, T. Rajeevakumar, K. Stawiasz\",\"doi\":\"10.1109/VTEST.1998.670841\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A \\\"system on a chip\\\" is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.\",\"PeriodicalId\":128521,\"journal\":{\"name\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"volume\":\"63 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1998.670841\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1998.670841","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A "system on a chip" is described, which integrates 16 Mbits of DRAM, digital logic, SRAM, three PLLs, and a triple video digital-to-analog converter in a 0.5 micron CMOS DRAM process. Application specific integrated circuit (ASIC) techniques are employed, using multiple DRAM macros with built-in self test (BIST), full level-sensitive scan design (LSSD) logic, and externally accessible analog circuitry. Issues regarding functional debugging, DRAM macro isolation and low cost manufacturing test using only a logic tester are described.
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