一种节能的完全集成的OOK收发器SoC,用于无线体域网络

Bo Zhao, Yinan Sun, Wei Zou, Y. Lian, Yongpan Liu, Huazhong Yang
{"title":"一种节能的完全集成的OOK收发器SoC,用于无线体域网络","authors":"Bo Zhao, Yinan Sun, Wei Zou, Y. Lian, Yongpan Liu, Huazhong Yang","doi":"10.1109/ASSCC.2013.6691077","DOIUrl":null,"url":null,"abstract":"This work presents a low-power high-speed system-on-chip (SoC) for wireless body area networks (WBANs). The SoC is fully integrated with a 10 Mb/s on-off keying (OOK) RF transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver adopts envelop detector (ED) based structure to improve the energy efficiency. Conventional ED based structure has a poor sensitivity when reaching a bit rate of Mb/s level. To resolve the problem, we design a receiving (Rx) front-end with 77 dB gain at 10 Mb/s data rate, and propose a novel supply isolation scheme to avoid the instability induced by such a high gain. The transmitter is based on a 2 GHz digitally controlled oscillator (DCO), which uses bond wires as inductors to further reduce the power at transmitting (Tx) mode. The digital baseband is designed by a near-threshold design (NTD) method for low power consumption. The chip is implemented with 0.13 μm CMOS technology, measured results show that the receiver consumes 0.214 nJ/bit at -65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of -5.4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"An energy efficient fully integrated OOK transceiver SoC for wireless body area networks\",\"authors\":\"Bo Zhao, Yinan Sun, Wei Zou, Y. Lian, Yongpan Liu, Huazhong Yang\",\"doi\":\"10.1109/ASSCC.2013.6691077\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a low-power high-speed system-on-chip (SoC) for wireless body area networks (WBANs). The SoC is fully integrated with a 10 Mb/s on-off keying (OOK) RF transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver adopts envelop detector (ED) based structure to improve the energy efficiency. Conventional ED based structure has a poor sensitivity when reaching a bit rate of Mb/s level. To resolve the problem, we design a receiving (Rx) front-end with 77 dB gain at 10 Mb/s data rate, and propose a novel supply isolation scheme to avoid the instability induced by such a high gain. The transmitter is based on a 2 GHz digitally controlled oscillator (DCO), which uses bond wires as inductors to further reduce the power at transmitting (Tx) mode. The digital baseband is designed by a near-threshold design (NTD) method for low power consumption. The chip is implemented with 0.13 μm CMOS technology, measured results show that the receiver consumes 0.214 nJ/bit at -65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of -5.4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6691077\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6691077","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5

摘要

本研究提出一种低功耗、高速的无线体域网路系统片上系统(SoC)。SoC完全集成了10mb /s的开关键控(OOK)射频收发器、数字处理单元、8051微控制单元(MCU)、逐次逼近(SAR) ADC等。接收机采用包络探测器(ED)结构,提高了能量利用率。传统的基于ED的结构在达到Mb/s级比特率时灵敏度较差。为了解决这个问题,我们设计了一个在10mb /s数据速率下具有77db增益的接收(Rx)前端,并提出了一种新的电源隔离方案,以避免如此高增益引起的不稳定性。发射器基于2 GHz的数字控制振荡器(DCO),它使用键合线作为电感,以进一步降低传输(Tx)模式的功率。采用近阈值设计(NTD)方法设计数字基带,实现低功耗。该芯片采用0.13 μm CMOS工艺实现,测量结果表明,在-65 dBm灵敏度下,接收器功耗为0.214 nJ/bit,在-5.4 dBm输出功率下,传输效率为0.285 nJ/bit。此外,数字基带的电源电压降至0.55 V时,功耗为34.8 pJ/bit,表明其每比特的能量降低到超阈值工作的近1/4。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
An energy efficient fully integrated OOK transceiver SoC for wireless body area networks
This work presents a low-power high-speed system-on-chip (SoC) for wireless body area networks (WBANs). The SoC is fully integrated with a 10 Mb/s on-off keying (OOK) RF transceiver, digital processing units, an 8051 micro-controlled unit (MCU), a successive approximation (SAR) ADC, and etc. The receiver adopts envelop detector (ED) based structure to improve the energy efficiency. Conventional ED based structure has a poor sensitivity when reaching a bit rate of Mb/s level. To resolve the problem, we design a receiving (Rx) front-end with 77 dB gain at 10 Mb/s data rate, and propose a novel supply isolation scheme to avoid the instability induced by such a high gain. The transmitter is based on a 2 GHz digitally controlled oscillator (DCO), which uses bond wires as inductors to further reduce the power at transmitting (Tx) mode. The digital baseband is designed by a near-threshold design (NTD) method for low power consumption. The chip is implemented with 0.13 μm CMOS technology, measured results show that the receiver consumes 0.214 nJ/bit at -65 dBm sensitivity, and the Tx energy efficiency is 0.285 nJ/bit at an output power of -5.4 dBm. In addition, the digital baseband consumes 34.8 pJ/bit with its supply voltage lowered to 0.55 V, indicating its energy per bit is reduced to nearly 1/4 of the super-threshold operation.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Future mobile society beyond Moore's Law A 691 Mbps 1.392mm2 configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS Collaborative innovation for future mobile applications A 0.5V 34.4uW 14.28kfps 105dB smart image sensor with array-level analog signal processing An 85mW 14-bit 150MS/s pipelined ADC with 71.3dB peak SNDR in 130nm CMOS
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1