创新实践环节3C:应对高速I/ o可测试性和调试的挑战

S. Shaikh
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摘要

随着VLSI技术、工艺、封装和架构的不断进步,SoC系统的复杂性不断增加。这导致了与高速IO (HSIO)电路相关的现代VLSI系统中设计错误,制造缺陷和客户退货的前所未有的增加。在未来的系统中,随着外形尺寸越来越小,集成复杂度越来越高,制造工艺越来越复杂,这种情况将会加剧。本次会议包括三个演讲,每个演讲都强调了hho的挑战,并描述了测试和调试的一些解决方案。
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Innovative practices session 3C: Harnessing the challenges of testability and debug of high speed I/Os
With increasing advances in VLSI technology, process, packaging and architecture, SoC systems continue to increase in complexity. This has resulted in an unprecedented increase in design errors, manufacturing flaws and customer returns in modern VLSI systems related to High Speed IO (HSIO) circuits. The situation will be exacerbated in future systems with increasingly smaller form factors, higher integration complexity, and more complex manufacturing process. This session comprises of three presentations each highlighting the challenges and describing a few solutions for test and debug of HSIOs.
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