On-chip ESD protection design by using polysilicon diodes in CMOS technology for smart card application

A novel on-chip ESD protection design using polysilicon diodes for a smart card application is reported in this paper. By adding an efficient V/sub DD/-to-V/sub SS/ clamp circuit, the HBM ESD level of the smart card IC with polysilicon diodes as the ESD protection devices have been successfully improved from the original /spl sim/300 V to become /spl ges/3 kV. Different process splits have been experimentally evaluated to find a suitable doping concentration for optimization of the polysilicon diodes for both smart card application and on-chip ESD protection design.