A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications

We report the highest sampling-rate single-chip ADC in any semiconductor technology. The circuit uses a 2x time-interleaved architecture integrating two track-and-hold amplifiers, each driving a 5-bit flash sub-ADC sampled at 64 GHz in antiphase. The digital outputs of the two sub-ADCs feed an on-die 128-GS/s thermometer-coded DAC whose sole purpose is for testing the ADC. The performance of the ADC-DAC combo, including the SFDR, and the ENOB of 4.1 bits up to 32-GHz input signals, was characterized on die and includes the impact of the DAC. The power consumption and layout footprint of the ADC, critical for operation at 128-GS/s, were minimized by employing novel 1-mA Cherry-Hooper comparators and quasi-CML MOS-HBT latches with active peaking, which reduced the footprint of each of the 64 ADC-lanes to $\mathbf{10}\mu\mathbf{m\ 70}\mu\mathbf{m}$. The total power consumption of the ADC is 1.25 W and the total die area of the ADC-DAC chip is $\mathbf{1.1}\mathbf{mm}\times\mathbf{1.9}\mathbf{mm}$.