CMOS高速数字数据处理器

1989 Proceedings of the IEEE Custom Integrated Circuits Conference Pub Date : 1989-05-15 DOI:10.1109/CICC.1989.56731

T. Komatsu, K. Watanabe, E. Minamimura, Y. Kowase, S. Ueda, N. Horie, S. Asai, T. Matsuura

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引用次数: 2

摘要

介绍了一种1.3 μm CMOS高速数字数据处理器(DDP)。该器件采用高速(15 MS/s) 7位半闪式模数转换器、数字波均衡器和数字锁相环。DDP有27 K晶体管，芯片尺寸为4.75×4.90 mm2，功耗为100mw

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CMOS high speed digital datastrobe processor

A 1.3-μm CMOS high-speed digital datastrobe processor (DDP) is described. This device uses a high-speed (15 MS/s) 7-bit half-flash analog-to-digital converter, a digital wave equalizer, and a digital phase-locked loop. The DDP has 27 K transistors in a 4.75×4.90 mm 2 chip size and consumes 100 mW

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1989 Proceedings of the IEEE Custom Integrated Circuits Conference

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