{"title":"基于fpga的维特比解码器的设计与实现","authors":"B. Pandita, S. Roy","doi":"10.1109/ICVD.1999.745223","DOIUrl":null,"url":null,"abstract":"This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed.","PeriodicalId":443373,"journal":{"name":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-01-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":"{\"title\":\"Design and implementation of a Viterbi decoder using FPGAs\",\"authors\":\"B. Pandita, S. Roy\",\"doi\":\"10.1109/ICVD.1999.745223\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed.\",\"PeriodicalId\":443373,\"journal\":{\"name\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"volume\":\"26 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-01-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"26\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICVD.1999.745223\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICVD.1999.745223","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of a Viterbi decoder using FPGAs
This paper describes the design at implementation of Viterbi decoder using FPGAs. In this paper we explore an FPGA based implementation methodology for rapidly prototyping designs. We use high level synthesis to achieve this. Some of the implementation issues related to the Viterbi decoder such as organization of path memory, decision memory reading techniques, and the clocking mechanism have been discussed.
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