Archit Shah, Sherman E. Peek, Bhargav Yelamanchili, Vaibhav Gupta, D. Tuckerman, C. Cantaloube, John A. Sellers, M. Hamilton
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引用次数: 3
摘要
我们描述了一种超导多芯片模块(S-MCM)技术,使用Mo作为坚固的衬底,在其上构建多层超导重分布层,用于芯片间信号传输,用于密集集成的低温和量子电子学。与目前可用的技术相比,Mo的机械坚固性和延展性可以允许在更大规模的S-MCM基板上集成芯片。我们通过使用In凸起和环氧底料将Si芯片倒装到Mo衬底来演示这种集成技术。超导菊链测试结构由Mo衬底与聚酰亚胺介质和超导Nb走线连接到具有不同跃迁数量和碰撞阵列密度的Si芯片形成。在室温至4.2 K范围内测量了不同雏菊链构型的电阻和超导转变温度。为了探索与cte相关的挑战,使用尺寸高达27 mm x 22 mm(凹凸阵列尺寸为20 mm x 20 mm)的Si芯片的组件被发现可以在从室温到低温的多个热循环中存活下来。
Superconducting Molybdenum Multi-Chip Module Approach for Cryogenic and Quantum Applications
We describe a superconducting multi-chip module (S-MCM) technology using Mo as a robust substrate on which to construct multi-layer superconducting redistribution layers for chip-to-chip signal transmission for densely-integrated cryogenic and quantum electronics. The mechanical robustness and ductile nature of Mo can allow for the integration of chips on a larger scale S-MCM substrate compared to currently available technologies. We demonstrate this integration technology by flip-chip bonding Si chips to Mo substrates using In bumps and epoxy underfill. Superconducting daisy-chain test structures were formed by Mo substrates with polyimide dielectric and superconducting Nb traces connected to Si chips with varying numbers of transitions and bump array densities. Resistance and superconducting transition temperatures of the various daisy-chain configurations were measured from room temperature to 4.2 K. To explore CTE-related challenges, assemblies using Si chips with dimensions up to 27 mm x 22 mm (In bump array size of 20 mm x 20 mm) were found to survive the multiple thermal cycles from room temperature to cryogenic temperatures.