Metalization process parasitic reduction by structure modeling

Summary form only given. A description is given of an effort to determine the effect of modifying metal process parameters, notably metal and dielectric thickness, to decrease propagation delay in the long metal lines found on many gate array and microprocessor devices. The method used involved the use of electrical, thermal, and structural simulation program ANSYS to calculate two-dimensional capacitance values for metal lines with differing thicknesses and widths and varying dielectric thicknesses. Results from the ANSYS models are then used to find empirical second-order equations to describe the relationship between each of the process variables and the metal line capacitance. These equations were then placed into the spread sheet program EXCEL, and different values of the process parameters were used to try to minimize the RC product of the metal line.<>