将内置自检应用于多数投票容错电路

C. Stroud, J. Tannehill
{"title":"将内置自检应用于多数投票容错电路","authors":"C. Stroud, J. Tannehill","doi":"10.1109/VTEST.1998.670884","DOIUrl":null,"url":null,"abstract":"Testing requirements for the application of built-in self-test to fault tolerant circuits include: (1) detection of all single and multiple faults and (2) verification of correct circuit operation in the presence of faults. Modifications to built-in logic block observer (BILBO) and circular BIST are proposed which make these techniques satisfy both testing requirements. Evaluation of the two modified BIST approaches via single and multiple stuck-at fault simulation in conjunction with a random fault injection procedure indicate that the modified BILBO approach provides better testing results.","PeriodicalId":128521,"journal":{"name":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Applying built-in self-test to majority voting fault tolerant circuits\",\"authors\":\"C. Stroud, J. Tannehill\",\"doi\":\"10.1109/VTEST.1998.670884\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Testing requirements for the application of built-in self-test to fault tolerant circuits include: (1) detection of all single and multiple faults and (2) verification of correct circuit operation in the presence of faults. Modifications to built-in logic block observer (BILBO) and circular BIST are proposed which make these techniques satisfy both testing requirements. Evaluation of the two modified BIST approaches via single and multiple stuck-at fault simulation in conjunction with a random fault injection procedure indicate that the modified BILBO approach provides better testing results.\",\"PeriodicalId\":128521,\"journal\":{\"name\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1998.670884\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1998.670884","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

将内置自检应用于容错电路的测试要求包括:(1)检测所有单个和多个故障;(2)在存在故障时验证正确的电路操作。对内置逻辑块观测器(BILBO)和循环BIST进行了改进,使这两种技术同时满足测试要求。通过单个和多个卡在故障模拟以及随机故障注入程序对两种改进的BIST方法进行评估,表明改进的BILBO方法提供了更好的测试结果。
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Applying built-in self-test to majority voting fault tolerant circuits
Testing requirements for the application of built-in self-test to fault tolerant circuits include: (1) detection of all single and multiple faults and (2) verification of correct circuit operation in the presence of faults. Modifications to built-in logic block observer (BILBO) and circular BIST are proposed which make these techniques satisfy both testing requirements. Evaluation of the two modified BIST approaches via single and multiple stuck-at fault simulation in conjunction with a random fault injection procedure indicate that the modified BILBO approach provides better testing results.
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