{"title":"展台融合:有效的位融合乘数与展台编码","authors":"Seokho Lee, Youngmin Kim","doi":"10.1109/ISOCC50952.2020.9332943","DOIUrl":null,"url":null,"abstract":"Recently, several attempts have been made to optimize Deep Neural Networks (DNNs) through various hardware acceleration methods. Among them, Bit Fusion, the dynamic bit-level fusion/decomposition hardware architecture, was noted. We introduce a new model structure, Booth Fusion, which makes dynamic bit-level operations more efficient by implementing Bit Fusion with booth encoding. Our design shows improvements in 16.4% for the number of LUT and 14.2% for throughput.","PeriodicalId":270577,"journal":{"name":"2020 International SoC Design Conference (ISOCC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2020-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding\",\"authors\":\"Seokho Lee, Youngmin Kim\",\"doi\":\"10.1109/ISOCC50952.2020.9332943\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recently, several attempts have been made to optimize Deep Neural Networks (DNNs) through various hardware acceleration methods. Among them, Bit Fusion, the dynamic bit-level fusion/decomposition hardware architecture, was noted. We introduce a new model structure, Booth Fusion, which makes dynamic bit-level operations more efficient by implementing Bit Fusion with booth encoding. Our design shows improvements in 16.4% for the number of LUT and 14.2% for throughput.\",\"PeriodicalId\":270577,\"journal\":{\"name\":\"2020 International SoC Design Conference (ISOCC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 International SoC Design Conference (ISOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISOCC50952.2020.9332943\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 International SoC Design Conference (ISOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISOCC50952.2020.9332943","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Booth Fusion: Efficient Bit Fusion Multiplier with Booth Encoding
Recently, several attempts have been made to optimize Deep Neural Networks (DNNs) through various hardware acceleration methods. Among them, Bit Fusion, the dynamic bit-level fusion/decomposition hardware architecture, was noted. We introduce a new model structure, Booth Fusion, which makes dynamic bit-level operations more efficient by implementing Bit Fusion with booth encoding. Our design shows improvements in 16.4% for the number of LUT and 14.2% for throughput.