{"title":"一个10.4-ENOB 120MS/s SAR ADC，在90nm CMOS上进行DAC线性校准","authors":"Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins","doi":"10.1109/ASSCC.2013.6690984","DOIUrl":null,"url":null,"abstract":"This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation.","PeriodicalId":296544,"journal":{"name":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS\",\"authors\":\"Yan Zhu, Chi-Hang Chan, U. Seng-Pan, R. Martins\",\"doi\":\"10.1109/ASSCC.2013.6690984\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation.\",\"PeriodicalId\":296544,\"journal\":{\"name\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-12-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2013.6690984\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Asian Solid-State Circuits Conference (A-SSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2013.6690984","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 10.4-ENOB 120MS/s SAR ADC with DAC linearity calibration in 90nm CMOS
This paper proposes a DAC linearity calibration and a phase-splitting bit register for a SAR ADC. The calibration corrects the conversion nonlinearity of the bridge DAC structure in the digital domain leading to higher accuracy and insensitivity to comparison offset. Moreover, a phase-splitting bit register is presented to optimize the speed of the digital circuitry. Measurements obtained from a 90nm CMOS prototype operating at 120MS/s and 1.2V supply achieve a SNDR of 64.3dB with 3.2mW power dissipation.
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