Ingvar Carlson, S. Anderson, S. Natarajan, A. Alvandpour
{"title":"高密度，低泄漏，5T SRAM用于嵌入式缓存","authors":"Ingvar Carlson, S. Anderson, S. Natarajan, A. Alvandpour","doi":"10.1109/ESSCIR.2004.1356656","DOIUrl":null,"url":null,"abstract":"This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV<Vcc=1.8 V. A 128 Kb memory, based on the 5T SRAM cell, has 23% smaller area, 75% lower bitline leakage, and a read/write performance comparable to a conventional 6T SRAM. The robustness of the design has been validated at worst-case process variations.","PeriodicalId":294077,"journal":{"name":"Proceedings of the 30th European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-11-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"104","resultStr":"{\"title\":\"A high density, low leakage, 5T SRAM for embedded caches\",\"authors\":\"Ingvar Carlson, S. Anderson, S. Natarajan, A. Alvandpour\",\"doi\":\"10.1109/ESSCIR.2004.1356656\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV<Vcc=1.8 V. A 128 Kb memory, based on the 5T SRAM cell, has 23% smaller area, 75% lower bitline leakage, and a read/write performance comparable to a conventional 6T SRAM. The robustness of the design has been validated at worst-case process variations.\",\"PeriodicalId\":294077,\"journal\":{\"name\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-11-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"104\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 30th European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIR.2004.1356656\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 30th European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIR.2004.1356656","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A high density, low leakage, 5T SRAM for embedded caches
This paper describes an embedded high density 128 Kb memory, utilizing a 5-transistor (5T) single bitline SRAM cell in a standard 0.18 /spl mu/m CMOS technology. The 5T-SRAM cell allows writing of '1', when the voltage at its single bitline is at Vcc. As a consequence, for a nondestructive read operation, the bitline is precharged to a voltage Vpc=600 mV
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