共晶晶贴合后GaN/Si界面射频损耗增加

K. Reiser, J. Twynam, H. Brech, S. Hardikar, R. Weigel
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引用次数: 1

摘要

研究了在高阻硅衬底上生长的AlGaN/GaN hemt的共晶贴片对射频衬底损耗的影响。在模具附着后,观察到负载拉效率的严重退化。分析了不同热膨胀系数的法兰上的模具的这种退化,发现衬底应变与载荷拉效率之间存在线性关系。共面波导(cpw)的损耗测量表明,随着应变的增加,衬底损耗增加,而晶体管导通电阻不受影响。因此,负载拉效率的下降归因于衬底损耗的增加。通过评估低频电容测量的偏置依赖性以及CPW特性的偏置依赖性,我们发现衬底损耗的增加可以通过GaN/Si界面上界面电荷的形成来解释。据我们所知,这是第一次证明GaN晶体管效率下降与传输线损耗和共晶芯片附着后GaN/Si界面的变化有关。
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Increased RF-Losses at the GaN/Si Interface after Eutectic Die Attach
The influence of eutectic die attach on RF-substrate losses of AlGaN/GaN HEMTs grown on high-resistivity silicon substrates has been studied. A severe degradation in load pull efficiency is observed after die attach. Analyzing this degradation for dies attached to flanges with differing thermal expansion coefficient shows a linear relationship between substrate strain and load pull efficiency. Loss measurements of coplanar waveguides (CPWs) show increasing substrate losses with increasing strain, while the transistor on-resistance remains unaffected. The degradation in load pull efficiency is, therefore, attributed to increased substrate losses. By evaluating the bias dependence of low frequency capacitance measurements together with the bias dependence of CPW characteristics, we show that the increase in substrate loss can be explained by the formation of interface charge at the GaN/Si interface. To the best of our knowledge, this is the first time that GaN transistor efficiency degradation has been shown to correlate with transmission line losses and changes at the GaN/Si interface after eutectic die attach.
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