HLS-centric DSE and Optimization for Dynamically Reconfigurable Elliptic Curve Cryptography (ReCC)

Asymmetric cryptography is frequently used for key exchanges and signatures in today's secure data transmissions, for instance, Elliptic Curve Cryptography (ECC). This paper describes our ECC-based cryptographic algorithms implementation on a low-end All Programmable System-on-Chip (APSoC) imposed upon its Dynamic Partial Reconfiguration (DPR) due to the target platform's limited resource. Our asymmetric cryptosystem is based on elliptic curves defined over prime fields and utilizes a dynamic change of multiple key lengths. High-Level Synthesis (HLS) is the basis of our Design Space Exploration (DSE) and hardware implementation. The design is adapted to be algorithmically robust against numerous existing types of attacks. Referring to various possible key lengths, the provided modes are 192, 256, 384, and 512 bits during the design time. An optimized result in design time shows an implementation of the key length of 512 bits is inapplicable due to FPGA resources' plethora in our targeted APSoC. An optimized design is implemented and compared to particularly related works. Indeed, DPR usage brings an advantage that resources can be reused for ECC with various key lengths, other implementable crypto algorithms, or non-crypto designs.